Age | Commit message (Expand) | Author | Files | Lines |
2020-01-24 | cpu: Use cpu_class_set_parent_reset() | Greg Kurz | 1 | -2/+1 |
2020-01-17 | Merge remote-tracking branch 'remotes/rth/tags/pull-or1k-20200116' into staging | Peter Maydell | 1 | -1/+1 |
2020-01-16 | target/openrisc: Fix FPCSR mask to allow setting DZF | Stafford Horne | 1 | -1/+1 |
2020-01-15 | tcg: Search includes from the project root source directory | Philippe Mathieu-Daudé | 1 | -1/+1 |
2019-10-28 | target/openrisc: fetch code with translator_ld | Emilio G. Cota | 1 | -1/+1 |
2019-09-04 | target/openrisc: Update cpu "any" to v1.3 | Richard Henderson | 1 | -1/+1 |
2019-09-04 | target/openrisc: Implement l.adrp | Richard Henderson | 3 | -0/+16 |
2019-09-04 | target/openrisc: Implement move to/from FPCSR | Richard Henderson | 5 | -5/+38 |
2019-09-04 | target/openrisc: Implement unordered fp comparisons | Richard Henderson | 5 | -0/+145 |
2019-09-04 | target/openrisc: Add support for ORFPX64A32 | Richard Henderson | 6 | -3/+332 |
2019-09-04 | target/openrisc: Check CPUCFG_OF32S for float insns | Richard Henderson | 2 | -50/+36 |
2019-09-04 | target/openrisc: Fix lf.ftoi.s | Richard Henderson | 1 | -1/+1 |
2019-09-04 | target/openrisc: Add VR2 and AVR special processor registers | Richard Henderson | 3 | -6/+19 |
2019-09-04 | target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init | Richard Henderson | 3 | -13/+22 |
2019-09-04 | target/openrisc: Make VR and PPC read-only | Richard Henderson | 2 | -12/+1 |
2019-09-04 | target/openrisc: Cache R0 in DisasContext | Richard Henderson | 1 | -7/+12 |
2019-09-04 | target/openrisc: Replace cpu register array with a function | Richard Henderson | 1 | -97/+116 |
2019-09-04 | target/openrisc: Add DisasContext parameter to check_r0_write | Richard Henderson | 1 | -47/+49 |
2019-09-03 | tcg: TCGMemOp is now accelerator independent MemOp | Tony Nguyen | 1 | -2/+2 |
2019-08-21 | hw/core: Move cpu.c, cpu.h from qom/ to hw/core/ | Markus Armbruster | 1 | -1/+1 |
2019-08-16 | Include hw/boards.h a bit less | Markus Armbruster | 1 | -1/+0 |
2019-08-16 | Include hw/hw.h exactly where needed | Markus Armbruster | 1 | -1/+0 |
2019-08-16 | migration: Move the VMStateDescription typedef to typedefs.h | Markus Armbruster | 1 | -1/+1 |
2019-07-05 | general: Replace global smp variables with smp machine properties | Like Xu | 1 | -1/+5 |
2019-06-12 | Include qemu-common.h exactly where needed | Markus Armbruster | 9 | -9/+0 |
2019-06-10 | cpu: Remove CPU_COMMON | Richard Henderson | 1 | -2/+0 |
2019-06-10 | cpu: Introduce CPUNegativeOffsetState | Richard Henderson | 1 | -1/+1 |
2019-06-10 | cpu: Introduce cpu_set_cpustate_pointers | Richard Henderson | 1 | -2/+1 |
2019-06-10 | cpu: Move ENV_OFFSET to exec/gen-icount.h | Richard Henderson | 1 | -1/+0 |
2019-06-10 | target/openrisc: Use env_cpu, env_archcpu | Richard Henderson | 3 | -12/+6 |
2019-06-10 | cpu: Replace ENV_GET_CPU with env_cpu | Richard Henderson | 1 | -2/+0 |
2019-06-10 | cpu: Define ArchCPU | Richard Henderson | 1 | -0/+1 |
2019-06-10 | cpu: Define CPUArchState with typedef | Richard Henderson | 1 | -2/+2 |
2019-06-10 | tcg: Split out target/arch/cpu-param.h | Richard Henderson | 2 | -11/+20 |
2019-05-10 | tcg: Use CPUClass::tlb_fill in cputlb.c | Richard Henderson | 1 | -6/+0 |
2019-05-10 | target/openrisc: Convert to CPUClass::tlb_fill | Richard Henderson | 3 | -36/+39 |
2019-05-08 | target/openrisc: Fix LGPL information in the file headers | Thomas Huth | 8 | -8/+8 |
2019-04-24 | tcg: Hoist max_insns computation to tb_gen_code | Richard Henderson | 1 | -2/+2 |
2019-04-18 | disas: Rename include/disas/bfd.h back to include/disas/dis-asm.h | Markus Armbruster | 1 | -1/+1 |
2019-04-18 | qom/cpu: Simplify how CPUClass:cpu_dump_state() prints | Markus Armbruster | 2 | -8/+6 |
2019-04-18 | target: Simplify how the TARGET_cpu_list() print | Markus Armbruster | 2 | -11/+6 |
2019-01-30 | target/openrisc: Fix LGPL version number | Thomas Huth | 7 | -7/+7 |
2018-11-27 | vmstate: constify VMStateField | Marc-André Lureau | 1 | -2/+3 |
2018-10-31 | decodetree: Remove "insn" argument from trans_* expanders | Richard Henderson | 2 | -112/+111 |
2018-07-03 | target/openrisc: Fix writes to interrupt mask register | Stafford Horne | 1 | -1/+1 |
2018-07-03 | target/openrisc: Fix delay slot exception flag to match spec | Stafford Horne | 1 | -7/+12 |
2018-07-03 | linux-user: Implement signals for openrisc | Richard Henderson | 1 | -0/+1 |
2018-07-03 | target/openrisc: Reorg tlb lookup | Richard Henderson | 2 | -170/+88 |
2018-07-03 | target/openrisc: Increase the TLB size | Richard Henderson | 3 | -6/+7 |
2018-07-03 | target/openrisc: Stub out handle_mmu_fault for softmmu | Richard Henderson | 1 | -30/+5 |