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path: root/target/openrisc/translate.c
AgeCommit message (Expand)AuthorFilesLines
2020-08-21meson: targetPaolo Bonzini1-1/+1
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini1-1/+1
2020-01-15tcg: Search includes from the project root source directoryPhilippe Mathieu-Daudé1-1/+1
2019-10-28target/openrisc: fetch code with translator_ldEmilio G. Cota1-1/+1
2019-09-04target/openrisc: Implement l.adrpRichard Henderson1-0/+13
2019-09-04target/openrisc: Implement unordered fp comparisonsRichard Henderson1-0/+85
2019-09-04target/openrisc: Add support for ORFPX64A32Richard Henderson1-0/+230
2019-09-04target/openrisc: Check CPUCFG_OF32S for float insnsRichard Henderson1-49/+35
2019-09-04target/openrisc: Cache R0 in DisasContextRichard Henderson1-7/+12
2019-09-04target/openrisc: Replace cpu register array with a functionRichard Henderson1-97/+116
2019-09-04target/openrisc: Add DisasContext parameter to check_r0_writeRichard Henderson1-47/+49
2019-09-03tcg: TCGMemOp is now accelerator independent MemOpTony Nguyen1-2/+2
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster1-1/+0
2019-04-24tcg: Hoist max_insns computation to tb_gen_codeRichard Henderson1-2/+2
2019-04-18qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster1-6/+5
2019-01-30target/openrisc: Fix LGPL version numberThomas Huth1-1/+1
2018-10-31decodetree: Remove "insn" argument from trans_* expandersRichard Henderson1-100/+100
2018-07-03target/openrisc: Fix cpu_mmu_indexRichard Henderson1-1/+1
2018-07-03target/openrisc: Form the spr index from tcgRichard Henderson1-7/+9
2018-07-03target/openrisc: Exit the TB after l.mtsprRichard Henderson1-1/+16
2018-07-03target/openrisc: Split out is_userRichard Henderson1-15/+12
2018-07-03target/openrisc: Link more translation blocksRichard Henderson1-41/+55
2018-07-03target/openrisc: Fix singlestep_enabledRichard Henderson1-18/+17
2018-07-03target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTBRichard Henderson1-3/+3
2018-07-03target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMPRichard Henderson1-4/+0
2018-07-03target/openrisc: Add print_insn_or1kRichard Henderson1-114/+0
2018-06-01tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson1-3/+3
2018-05-14target/openrisc: Merge disas_openrisc_insnRichard Henderson1-9/+4
2018-05-14target/openrisc: Convert dec_floatRichard Henderson1-230/+128
2018-05-14target/openrisc: Convert dec_compiRichard Henderson1-58/+58
2018-05-14target/openrisc: Convert dec_compRichard Henderson1-62/+58
2018-05-14target/openrisc: Convert dec_MRichard Henderson1-28/+13
2018-05-14target/openrisc: Convert dec_logicRichard Henderson1-36/+26
2018-05-14target/openrisc: Convert dec_macRichard Henderson1-33/+22
2018-05-14target/openrisc: Convert dec_calcRichard Henderson1-149/+173
2018-05-14target/openrisc: Convert remainder of dec_misc insnsRichard Henderson1-149/+110
2018-05-14target/openrisc: Convert memory insnsRichard Henderson1-139/+136
2018-05-14target/openrisc: Convert branch insnsRichard Henderson1-78/+72
2018-05-14target/openrisc: Start conversion to decodetree.pyRichard Henderson1-43/+41
2018-05-14target-openrisc: Write back result before FPE exceptionRichard Henderson1-36/+65
2018-05-09target/openrisc: convert to TranslatorOpsEmilio G. Cota1-84/+79
2018-05-09target/openrisc: convert to DisasContextBaseEmilio G. Cota1-47/+46
2017-10-27Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell1-1/+1
2017-10-25disas: Remove unused flags argumentsRichard Henderson1-1/+1
2017-10-24tcg: Initialize cpu_env genericallyRichard Henderson1-3/+0
2017-10-24tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota1-1/+1
2017-10-24tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota1-3/+3
2017-09-06target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova1-0/+6
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova1-2/+2
2017-05-04target/openrisc: implement shadow registersStafford Horne1-2/+3
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