riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-10-21	openrisc/cputimer: Perparation for Multicore	Stafford Horne	1	-2/+2
2017-10-21	target/openrisc: Make coreid and numcores variable	Stafford Horne	1	-2/+3
2017-05-04	target/openrisc: Support non-busy idle state using PMR SPR	Stafford Horne	1	-0/+13
2017-05-04	target/openrisc: implement shadow registers	Stafford Horne	1	-0/+9
2017-05-04	target/openrisc: add numcores and coreid support	Stafford Horne	1	-0/+6
2017-04-21	target/openrisc: Implement EVBAR register	Tim 'mithro' Ansell	1	-0/+7
2017-02-14	target/openrisc: Tidy handling of delayed branches	Richard Henderson	1	-1/+1
2017-02-14	target/openrisc: Tidy ppc/npc implementation	Richard Henderson	1	-28/+16
2017-02-14	target/openrisc: Represent MACHI:MACLO as a single unit	Richard Henderson	1	-0/+13
2017-02-14	target/openrisc: Keep SR_F in a separate variable	Richard Henderson	1	-3/+2
2017-01-13	cputlb: drop flush_global flag from tlb_flush	Alex Bennée	1	-1/+1
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	1	-0/+288