riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-09-04	target/openrisc: Fix memory reading in debugger	Stafford Horne	1	-1/+7
2022-02-21	exec/exec-all: Move 'qemu/log.h' include in units requiring it	Philippe Mathieu-Daudé	1	-0/+1
2021-11-02	target/openrisc: Make openrisc_cpu_tlb_fill sysemu only	Richard Henderson	1	-9/+0
2019-06-12	Include qemu-common.h exactly where needed	Markus Armbruster	1	-1/+0
2019-05-10	tcg: Use CPUClass::tlb_fill in cputlb.c	Richard Henderson	1	-6/+0
2019-05-10	target/openrisc: Convert to CPUClass::tlb_fill	Richard Henderson	1	-31/+34
2019-05-08	target/openrisc: Fix LGPL information in the file headers	Thomas Huth	1	-1/+1
2018-07-03	target/openrisc: Reorg tlb lookup	Richard Henderson	1	-162/+88
2018-07-03	target/openrisc: Stub out handle_mmu_fault for softmmu	Richard Henderson	1	-30/+5
2018-07-03	target/openrisc: Use identical sizes for ITLB and DTLB	Richard Henderson	1	-2/+2
2018-07-03	target/openrisc: Fix cpu_mmu_index	Richard Henderson	1	-3/+30
2018-07-03	target/openrisc: Reduce tlb to a single dimension	Richard Henderson	1	-14/+16
2018-07-03	target/openrisc: Merge mmu_helper.c into mmu.c	Richard Henderson	1	-0/+11
2018-07-03	target/openrisc: Remove indirect function calls for mmu	Richard Henderson	1	-39/+29
2018-07-03	target/openrisc: Merge tlb allocation into CPUOpenRISCState	Richard Henderson	1	-18/+16
2018-01-25	accel/tcg: add size paremeter in tlb_fill()	Laurent Vivier	1	-4/+4
2017-05-04	target/openrisc: Fixes for memory debugging	Stafford Horne	1	-4/+20
2017-02-14	target/openrisc: Implement lwa, swa	Richard Henderson	1	-0/+1
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	1	-0/+238