| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2017-05-04 | target/openrisc: Support non-busy idle state using PMR SPR | Stafford Horne | 1 | -0/+2 |
| 2017-04-21 | target/openrisc: Implement EPH bit | Tim 'mithro' Ansell | 1 | -0/+3 |
| 2017-04-21 | target/openrisc: Implement EVBAR register | Tim 'mithro' Ansell | 1 | -1/+5 |
| 2017-02-14 | target/openrisc: Tidy handling of delayed branches | Richard Henderson | 1 | -2/+2 |
| 2017-02-14 | target/openrisc: Keep SR_F in a separate variable | Richard Henderson | 1 | -1/+1 |
| 2017-02-14 | target/openrisc: Implement lwa, swa | Richard Henderson | 1 | -0/+1 |
| 2017-02-14 | target/openrisc: Fix exception handling status registers | Stafford Horne | 1 | -0/+7 |
| 2017-01-13 | cputlb: drop flush_global flag from tlb_flush | Alex Bennée | 1 | -1/+1 |
| 2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth | 1 | -0/+87 |
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index : riscv-gnu-toolchain/qemu.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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