| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2020-01-16 | target/openrisc: Fix FPCSR mask to allow setting DZF | Stafford Horne | 1 | -1/+1 |
| 2019-09-04 | target/openrisc: Implement move to/from FPCSR | Richard Henderson | 1 | -0/+13 |
| 2019-09-04 | target/openrisc: Implement unordered fp comparisons | Richard Henderson | 1 | -0/+20 |
| 2019-09-04 | target/openrisc: Add support for ORFPX64A32 | Richard Henderson | 1 | -2/+12 |
| 2019-09-04 | target/openrisc: Fix lf.ftoi.s | Richard Henderson | 1 | -1/+1 |
| 2019-05-08 | target/openrisc: Fix LGPL information in the file headers | Thomas Huth | 1 | -1/+1 |
| 2018-05-14 | target-openrisc: Write back result before FPE exception | Richard Henderson | 1 | -203/+49 |
| 2018-02-21 | target/*/cpu.h: remove softfloat.h | Alex Bennée | 1 | -0/+1 |
| 2017-02-14 | target/openrisc: Fix madd | Richard Henderson | 1 | -44/+24 |
| 2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth | 1 | -0/+301 |
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index : riscv-gnu-toolchain/qemu.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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