| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2019-06-10 | target/openrisc: Use env_cpu, env_archcpu | Richard Henderson | 1 | -3/+2 |
| 2019-05-08 | target/openrisc: Fix LGPL information in the file headers | Thomas Huth | 1 | -1/+1 |
| 2017-12-18 | misc: remove duplicated includes | Philippe Mathieu-Daudé | 1 | -1/+0 |
| 2017-02-14 | target/openrisc: Optimize for r0 being zero | Richard Henderson | 1 | -0/+1 |
| 2017-02-14 | target/openrisc: Keep SR_CY and SR_OV in a separate variables | Richard Henderson | 1 | -6/+25 |
| 2017-02-14 | target/openrisc: Put SR[OVE] in TB flags | Richard Henderson | 1 | -1/+1 |
| 2017-02-14 | target/openrisc: Streamline arithmetic and OVE | Richard Henderson | 1 | -0/+12 |
| 2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth | 1 | -0/+30 |
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index : riscv-gnu-toolchain/qemu.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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