riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-02-21	target/*/cpu.h: remove softfloat.h	Alex Bennée	1	-1/+0
2018-01-25	accel/tcg: add size paremeter in tlb_fill()	Laurent Vivier	1	-1/+1
2017-10-27	openrisc: cleanup cpu type name composition	Igor Mammedov	1	-0/+3
2017-10-21	openrisc/cputimer: Perparation for Multicore	Stafford Horne	1	-1/+3
2017-09-01	openrisc: replace cpu_openrisc_init() with cpu_generic_init()	Igor Mammedov	1	-3/+1
2017-05-04	target/openrisc: Support non-busy idle state using PMR SPR	Stafford Horne	1	-0/+10
2017-05-04	target/openrisc: Remove duplicate features property	Stafford Horne	1	-14/+2
2017-05-04	target/openrisc: implement shadow registers	Stafford Horne	1	-2/+13
2017-04-21	target/openrisc: Implement EVBAR register	Tim 'mithro' Ansell	1	-0/+7
2017-02-14	target/openrisc: Optimize for r0 being zero	Richard Henderson	1	-1/+4
2017-02-14	target/openrisc: Tidy handling of delayed branches	Richard Henderson	1	-7/+5
2017-02-14	target/openrisc: Tidy ppc/npc implementation	Richard Henderson	1	-1/+1
2017-02-14	target/openrisc: Fix madd	Richard Henderson	1	-3/+0
2017-02-14	target/openrisc: Represent MACHI:MACLO as a single unit	Richard Henderson	1	-2/+1
2017-02-14	target/openrisc: Keep SR_CY and SR_OV in a separate variables	Richard Henderson	1	-3/+10
2017-02-14	target/openrisc: Keep SR_F in a separate variable	Richard Henderson	1	-2/+13
2017-02-14	target/openrisc: Put SR[OVE] in TB flags	Richard Henderson	1	-2/+2
2017-02-14	target/openrisc: Implement lwa, swa	Richard Henderson	1	-0/+3
2017-02-14	target/openrisc: Rename the cpu from or32 to or1k	Richard Henderson	1	-1/+1
2017-01-13	qom/cpu: move tlb_flush to cpu_common_reset	Alex Bennée	1	-0/+3
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	1	-0/+411