| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2017-02-14 | target/openrisc: Optimize for r0 being zero | Richard Henderson | 1 | -1/+4 |
| 2017-02-14 | target/openrisc: Tidy handling of delayed branches | Richard Henderson | 1 | -7/+5 |
| 2017-02-14 | target/openrisc: Tidy ppc/npc implementation | Richard Henderson | 1 | -1/+1 |
| 2017-02-14 | target/openrisc: Fix madd | Richard Henderson | 1 | -3/+0 |
| 2017-02-14 | target/openrisc: Represent MACHI:MACLO as a single unit | Richard Henderson | 1 | -2/+1 |
| 2017-02-14 | target/openrisc: Keep SR_CY and SR_OV in a separate variables | Richard Henderson | 1 | -3/+10 |
| 2017-02-14 | target/openrisc: Keep SR_F in a separate variable | Richard Henderson | 1 | -2/+13 |
| 2017-02-14 | target/openrisc: Put SR[OVE] in TB flags | Richard Henderson | 1 | -2/+2 |
| 2017-02-14 | target/openrisc: Implement lwa, swa | Richard Henderson | 1 | -0/+3 |
| 2017-02-14 | target/openrisc: Rename the cpu from or32 to or1k | Richard Henderson | 1 | -1/+1 |
| 2017-01-13 | qom/cpu: move tlb_flush to cpu_common_reset | Alex Bennée | 1 | -0/+3 |
| 2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth | 1 | -0/+411 |
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index : riscv-gnu-toolchain/qemu.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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