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2019-07-03Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jul-02-2019' ↵Peter Maydell2-274/+483
into staging MIPS queue for July 2nd, 2019 # gpg: Signature made Tue 02 Jul 2019 17:09:29 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-jul-02-2019: target/mips: Correct helper for MSA FCLASS.<W|D> instructions target/mips: Unroll loops for MSA float max/min instructions target/mips: Correct comments in msa_helper.c target/mips: Correct comments in translate.c tcg/tests: target/mips: Correct MSA test compilation and execution order tcg/tests: target/mips: Amend MSA integer multiply tests tcg/tests: target/mips: Amend MSA fixed point multiply tests hw/mips: Express dependencies of the r4k platform with Kconfig hw/mips: Express dependencies of the Jazz machine with Kconfig hw/mips: Express dependencies of the MIPSsim machine with Kconfig hw/mips: Explicit the semi-hosting feature is always required tests/machine-none: Test recent MIPS cpus Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-02target/mips: Correct helper for MSA FCLASS.<W|D> instructionsAleksandar Markovic1-1/+3
Correct helper for MSA FCLASS.<W|D> instructions. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1562068213-11307-8-git-send-email-aleksandar.markovic@rt-rk.com>
2019-07-02target/mips: Unroll loops for MSA float max/min instructionsAleksandar Markovic1-73/+125
Slight preformance improvement for MSA float max/min instructions. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1562068213-11307-7-git-send-email-aleksandar.markovic@rt-rk.com>
2019-07-02target/mips: Correct comments in msa_helper.cAleksandar Markovic1-17/+41
Fix some errors in comments for MSA helpers. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1562068213-11307-6-git-send-email-aleksandar.markovic@rt-rk.com>
2019-07-02target/mips: Correct comments in translate.cAleksandar Markovic1-183/+314
Fix some checkpatch comment-related warnings. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <1562068213-11307-5-git-send-email-aleksandar.markovic@rt-rk.com>
2019-07-02qapi: Split machine-target.json off target.json and misc.jsonMarkus Armbruster1-1/+1
Move commands query-cpu-definitions, query-cpu-model-baseline, query-cpu-model-comparison, and query-cpu-model-expansion with their types from target.json to machine-target.json. Also move types CpuModelInfo, CpuModelExpansionType, and CpuModelCompareResult from misc.json there. Add machine-target.json to MAINTAINERS section "Machine core". Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190619201050.19040-13-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> [Commit message typo fixed]
2019-06-26target/mips: Fix big endian host behavior for interleave MSA instructionsAleksandar Markovic1-12/+12
Fix big endian host behavior for interleave MSA instructions. Previous fix used TARGET_WORDS_BIGENDIAN instead of HOST_WORDS_BIGENDIAN, which was a mistake. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561543629-20327-9-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-21Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-jun-21-2019' ↵Peter Maydell2-190/+403
into staging MIPS queue for June 21st, 2019 # gpg: Signature made Fri 21 Jun 2019 10:46:57 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-jun-21-2019: target/mips: Fix emulation of ILVR.<B|H|W> on big endian host target/mips: Fix emulation of ILVL.<B|H|W> on big endian host target/mips: Fix emulation of ILVOD.<B|H|W> on big endian host target/mips: Fix emulation of ILVEV.<B|H|W> on big endian host tests/tcg: target/mips: Amend tests for MSA pack instructions tests/tcg: target/mips: Include isa/ase and group name in test output target/mips: Fix if-else-switch-case arms checkpatch errors in translate.c target/mips: Fix some space checkpatch errors in translate.c MAINTAINERS: Consolidate MIPS disassembler-related items MAINTAINERS: Update file items for MIPS Malta board Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-21target/mips: Fix emulation of ILVR.<B|H|W> on big endian hostAleksandar Markovic1-0/+37
Fix emulation of ILVR.<B|H|W> on big endian host by applying mapping of data element indexes from one endian to another. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561038349-17105-5-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-21target/mips: Fix emulation of ILVL.<B|H|W> on big endian hostAleksandar Markovic1-0/+37
Fix emulation of ILVL.<B|H|W> on big endian host by applying mapping of data element indexes from one endian to another. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561038349-17105-4-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-21target/mips: Fix emulation of ILVOD.<B|H|W> on big endian hostAleksandar Markovic1-0/+37
Fix emulation of ILVOD.<B|H|W> on big endian host by applying mapping of data element indexes from one endian to another. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561038349-17105-3-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-21target/mips: Fix emulation of ILVEV.<B|H|W> on big endian hostAleksandar Markovic1-0/+37
Fix emulation of ILVEV.<B|H|W> on big endian host by applying mapping of data element indexes from one endian to another. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1561038349-17105-2-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-21target/mips: Fix if-else-switch-case arms checkpatch errors in translate.cAleksandar Markovic1-72/+133
Remove if-else-switch-case-arms-related checkpatch errors. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <1561037595-14413-5-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-21target/mips: Fix some space checkpatch errors in translate.cAleksandar Markovic1-118/+122
Remove some space-related checkpatch warning. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <1561037595-14413-4-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-21KVM: Introduce kvm_arch_destroy_vcpu()Liran Alon1-0/+5
Simiar to how kvm_init_vcpu() calls kvm_arch_init_vcpu() to perform arch-dependent initialisation, introduce kvm_arch_destroy_vcpu() to be called from kvm_destroy_vcpu() to perform arch-dependent destruction. This was added because some architectures (Such as i386) currently do not free memory that it have allocated in kvm_arch_init_vcpu(). Suggested-by: Maran Wilson <maran.wilson@oracle.com> Reviewed-by: Maran Wilson <maran.wilson@oracle.com> Signed-off-by: Liran Alon <liran.alon@oracle.com> Message-Id: <20190619162140.133674-3-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster3-3/+0
No header includes qemu-common.h after this commit, as prescribed by qemu-common.h's file comment. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190523143508.25387-5-armbru@redhat.com> [Rebased with conflicts resolved automatically, except for include/hw/arm/xlnx-zynqmp.h hw/arm/nrf51_soc.c hw/arm/msf2-soc.c block/qcow2-refcount.c block/qcow2-cluster.c block/qcow2-cache.c target/arm/cpu.h target/lm32/cpu.h target/m68k/cpu.h target/mips/cpu.h target/moxie/cpu.h target/nios2/cpu.h target/openrisc/cpu.h target/riscv/cpu.h target/tilegx/cpu.h target/tricore/cpu.h target/unicore32/cpu.h target/xtensa/cpu.h; bsd-user/main.c and net/tap-bsd.c fixed up]
2019-06-12Include qemu/module.h where needed, drop it from qemu-common.hMarkus Armbruster1-1/+1
Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190523143508.25387-4-armbru@redhat.com> [Rebased with conflicts resolved automatically, except for hw/usb/dev-hub.c hw/misc/exynos4210_rng.c hw/misc/bcm2835_rng.c hw/misc/aspeed_scu.c hw/display/virtio-vga.c hw/arm/stm32f205_soc.c; ui/cocoa.m fixed up]
2019-06-10cpu: Remove CPU_COMMONRichard Henderson1-2/+0
This macro is now always empty, so remove it. This leaves the entire contents of CPUArchState under the control of the guest architecture. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-10cpu: Introduce CPUNegativeOffsetStateRichard Henderson1-0/+1
Nothing in there so far, but all of the plumbing done within the target ArchCPU state. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-10cpu: Introduce cpu_set_cpustate_pointersRichard Henderson1-2/+1
Consolidate some boilerplate from foo_cpu_initfn. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-10cpu: Move ENV_OFFSET to exec/gen-icount.hRichard Henderson1-1/+0
Now that we have ArchCPU, we can define this generically, in the one place that needs it. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-10target/mips: Use env_cpu, env_archcpuRichard Henderson5-34/+18
Cleanup in the boilerplate that each target must define. Replace mips_env_get_cpu with env_archcpu. The combination CPU(mips_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-10cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson1-2/+0
Now that we have both ArchCPU and CPUArchState, we can define this generically instead of via macro in each target's cpu.h. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-10cpu: Define ArchCPURichard Henderson1-0/+1
For all targets, do this just before including exec/cpu-all.h. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-10cpu: Define CPUArchState with typedefRichard Henderson1-4/+2
For all targets, do this just before including exec/cpu-all.h. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-10tcg: Split out target/arch/cpu-param.hRichard Henderson3-17/+30
For all targets, into this new file move TARGET_LONG_BITS, TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS, TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES. Include this new file from exec/cpu-defs.h. This now removes the somewhat odd requirement that target/arch/cpu.h defines TARGET_LONG_BITS before including exec/cpu-defs.h, so push the bulk of the includes within target/arch/cpu.h to the top. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-07target/mips: Unroll loops in helpers for MSA logic instructionsAleksandar Markovic1-4/+40
Unroll loops in helpers for MSA logic instructions for better performance. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-5-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-07target/mips: Outline places for future MSA helpersAleksandar Markovic1-0/+461
Outline places for future MSA helpers to follow the same organization as in MSA tests. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-4-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-06target/mips: Fix block-comment-related issues in msa_helper.cAleksandar Markovic1-15/+27
Fix block-comment-related issues reported by checkpatch for file msa_helper.c. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-3-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-06target/mips: Fix space-related format issues in msa_helper.cAleksandar Markovic1-14/+14
Fix space-related format issues reported by checkpatch in file msa_helper.c. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1559838440-9866-2-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-01target/mips: Improve performance of certain MSA instructionsMateja Marjanovic1-109/+433
Eliminate loops for better performance. Following MSA instructions from "UNOP" group are affected: - NLZC.<B|H|W|D> - NLOC.<B|H|W|D> - PCNT.<B|H|W|D> Following MSA instructions from "BINOP" group are affected: - ADD_A.<B|H|W|D> - ADDS_A.<B|H|W|D> - ADDS_S.<B|H|W|D> - ADDS_U.<B|H|W|D> - ADDV.<B|H|W|D> - ASUB_S.<B|H|W|D> - ASUB_U.<B|H|W|D> - AVE_S.<B|H|W|D> - AVE_U.<B|H|W|D> - AVER_S.<B|H|W|D> - AVER_U.<B|H|W|D> - BCLR.<B|H|W|D> - BNEG.<B|H|W|D> - BSET.<B|H|W|D> - CEQ.<B|H|W|D> - CLE_S.<B|H|W|D> - CLE_U.<B|H|W|D> - CLT_S.<B|H|W|D> - CLT_U.<B|H|W|D> - DIV_S.<B|H|W|D> - DIV_U.<B|H|W|D> - DOTP_S.<B|H|W|D> - DOTP_U.<B|H|W|D> - HADD_S.<B|H|W|D> - HADD_U.<B|H|W|D> - HSUB_S.<B|H|W|D> - HSUB_U.<B|H|W|D> - MAX_A.<B|H|W|D> - MAX_S.<B|H|W|D> - MAX_U.<B|H|W|D> - MIN_A.<B|H|W|D> - MIN_S.<B|H|W|D> - MIN_U.<B|H|W|D> - MOD_S.<B|H|W|D> - MOD_U.<B|H|W|D> - MUL_Q.<B|H|W|D> - MULR_Q.<B|H|W|D> - MULV.<B|H|W|D> - SLL.<B|H|W|D> - SRA.<B|H|W|D> - SRAR.<B|H|W|D> - SRL.<B|H|W|D> - SRLR.<B|H|W|D> - SUBS_S.<B|H|W|D> - SUBS_U.<B|H|W|D> - SUBSUS_U.<B|H|W|D> - SUBSUU_S.<B|H|W|D> - SUBV.<B|H|W|D> Following MSA instructions from "TEROP" group are affected: - BINSL.<B|H|W|D> - BINSR.<B|H|W|D> - DPADD_S.<B|H|W|D> - DPADD_U.<B|H|W|D> - DPSUB_S.<B|H|W|D> - DPSUB_U.<B|H|W|D> - MADD_Q.<B|H|W|D> - MADDR_Q.<B|H|W|D> - MADDV.<B|H|W|D> - MSUB_Q.<B|H|W|D> - MSUBR_Q.<B|H|W|D> - MSUBV.<B|H|W|D> Additionally, following MSA instructionas are also affected: - ILVL.<B|H|W|D> - ILVR.<B|H|W|D> - ILVEV.<B|H|W|D> - ILVOD.<B|H|W|D> - PCKEV.<B|H|W|D> - PCKOD.<B|H|W|D> Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1551718283-4487-2-git-send-email-mateja.marjanovic@rt-rk.com>
2019-06-01target/mips: Clean up lmi_helper.cAleksandar Markovic1-3/+5
Remove several minor checkpatch warnings and errors. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <1556018982-3715-7-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-01target/mips: Clean up dsp_helper.cAleksandar Markovic1-11/+29
Remove several minor checkpatch warnings and errors. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <1556018982-3715-6-git-send-email-aleksandar.markovic@rt-rk.com>
2019-06-01target/mips: Add emulation of MMI instruction PCPYUDMateja Marjanovic1-1/+42
Add emulation of MMI instruction PCPYUD. The emulation is implemented using TCG front end operations directly to achieve better performance. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551712405-2530-4-git-send-email-mateja.marjanovic@rt-rk.com>
2019-06-01target/mips: Add emulation of MMI instruction PCPYLDMateja Marjanovic1-1/+42
Add emulation of MMI instruction PCPYLD. The emulation is implemented using TCG front end operations directly to achieve better performance. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551712405-2530-3-git-send-email-mateja.marjanovic@rt-rk.com>
2019-06-01target/mips: Add emulation of MMI instruction PCPYHMateja Marjanovic1-1/+65
Add emulation of MMI instruction PCPYH. The emulation is implemented using TCG front end operations directly to achieve better performance. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551712405-2530-2-git-send-email-mateja.marjanovic@rt-rk.com>
2019-05-28Merge remote-tracking branch ↵Peter Maydell4-9/+20
'remotes/stsquad/tags/pull-testing-next-280519-2' into staging Various testing updates - semihosting re-factor (used in system tests) - aarch64 and alpha system tests - editorconfig tweak for .S - some docker image updates - iotests clean-up (without make check inclusion) # gpg: Signature made Tue 28 May 2019 17:26:34 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-next-280519-2: (27 commits) tests/qemu-iotests: re-format output to for make check-block tests/qemu-iotests/group: Re-use the "auto" group for tests that can always run Makefile.target: support per-target coverage reports Makefile: include per-target build directories in coverage report Makefile: fix coverage-report reference to BUILD_DIR .travis.yml: enable aarch64-softmmu and alpha-softmmu tcg tests tests/tcg/alpha: add system boot.S tests/tcg/multiarch: expand system memory test to cover more tests/tcg/minilib: support %c format char tests/tcg/multiarch: move the system memory test tests/tcg/aarch64: add system boot.S editorconfig: add settings for .s/.S files tests/tcg/multiarch: add hello world system test tests/tcg/multiarch: add support for multiarch system tests tests/docker: Test more components on the Fedora default image tests/docker: add ubuntu 18.04 MAINTAINERS: update for semihostings new home target/mips: convert UHI_plog to use common semihosting code target/mips: only build mips-semi for softmmu target/arm: correct return values for WRITE/READ in arm-semi ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-05-28target/mips: convert UHI_plog to use common semihosting codeAlex Bennée1-6/+6
Rather than printing directly to stdout lets use our common semihosting code. There is one minor difference in that the output currently defaults to stderr instead of stdout however this can be controlled by connecting semihosting to a chardev. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-05-28target/mips: only build mips-semi for softmmuAlex Bennée3-1/+12
The is_uhi gates all semihosting calls and always returns false for CONFIG_USER_ONLY builds. There is no reason to build and link mips-semi for these builds so lets fix that. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-28semihosting: move semihosting configuration into its own directoryAlex Bennée2-2/+2
In preparation for having some more common semihosting code let's excise the current config magic from vl.c into its own file. We shall later add more conditionals to the build configurations so we can avoid building this if we don't need it. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-26target/mips: realign comments to fix checkpatch warningsJules Irenge1-12/+22
Realign comments to fix warnings issued by checkpatc.pl tool "WARNING: Block comments use a leading /* on a separate line" within "target/mips/cpu.h" file. Signed-off-by: Jules Irenge <jbi.octave@gmail.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190413202818.13622-3-jbi.octave@gmail.com>
2019-05-26target/mips: add or remove space to fix checkpatch errorsJules Irenge1-81/+94
Add or remove space to fix errors issued by checkpatch.pl tool "ERROR: spaces required around that..." "ERROR: space required after that..." "ERROR: space required before the open parenthesis" "ERROR: space required after that..." "ERROR: space prohibited between function name and open parenthesis" "ERROR: code indent should never use tabs" "ERROR: line over 90 characters" within "target/mips/cpu.h" file. Signed-off-by: Jules Irenge <jbi.octave@gmail.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <20190413202818.13622-2-jbi.octave@gmail.com>
2019-05-26mips: Decide to map PAGE_EXEC in map_addressJakub Jermář1-5/+8
This commit addresses QEMU Bug #1825311: mips_cpu_handle_mmu_fault renders all accessed pages executable It allows finer-grained control over whether the accessed page should be executable by moving the decision to the underlying map_address function, which has more information for this. As a result, pages that have the XI bit set in the TLB and are accessed for read/write, don't suddenly end up being executable. Fixes: https://bugs.launchpad.net/qemu/+bug/1825311 Fixes: 2fb58b73746e ('target-mips: add RI and XI fields to TLB entry') Signed-off-by: Jakub Jermář <jakub.jermar@kernkonzept.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190517123533.868479-1-jakub.jermar@kernkonzept.com>
2019-05-26target/mips: Refactor and fix INSERT.<B|H|W|D> instructionsMateja Marjanovic3-18/+71
The old version of the helper for the INSERT.<B|H|W|D> MSA instructions has been replaced with four helpers that don't use switch, and change the endianness of the given index, when executed on a big endian host. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554212605-16457-6-git-send-email-mateja.marjanovic@rt-rk.com>
2019-05-26target/mips: Refactor and fix COPY_U.<B|H|W> instructionsMateja Marjanovic3-21/+59
The old version of the helper for the COPY_U.<B|H|W> MSA instructions has been replaced with four helpers that don't use switch, and change the endianness of the given index, when executed on a big endian host. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554212605-16457-5-git-send-email-mateja.marjanovic@rt-rk.com>
2019-05-26target/mips: Refactor and fix COPY_S.<B|H|W|D> instructionsMateja Marjanovic3-21/+67
The old version of the helper for the COPY_S.<B|H|W|D> MSA instructions has been replaced with four helpers that don't use switch, and change the endianness of the given index, when executed on a big endian host. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554212605-16457-4-git-send-email-mateja.marjanovic@rt-rk.com>
2019-05-26target/mips: Fix MSA instructions ST.<B|H|W|D> on big endian hostMateja Marjanovic1-20/+180
Fix the case when the host is a big endian machine, and change the approach toward ST.<B|H|W|D> instruction helpers. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554212605-16457-3-git-send-email-mateja.marjanovic@rt-rk.com>
2019-05-26target/mips: Fix MSA instructions LD.<B|H|W|D> on big endian hostMateja Marjanovic1-20/+168
Fix the case when the host is a big endian machine, and change the approach toward LD.<B|H|W|D> instruction helpers. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554212605-16457-2-git-send-email-mateja.marjanovic@rt-rk.com>
2019-05-26target/mips: Make the results of MOD_<U|S>.<B|H|W|D> the same as on hardwareMateja Marjanovic1-2/+2
MSA instructions MOD_<U|S>.<B|H|W|D> when dividing by zero, didn't return the same value when executed on a referent hardware (FPGA MIPS 64 r6, little endian) and when executed on QEMU, which is not a real bug, because the result when dividing by zero is UNPREDICTABLE [1] (page 255, 256). [1] MIPS Architecture for Programmers Volume IV-j: The MIPS64 SIMD Architecture Module, Revision 1.12 Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554207110-9113-3-git-send-email-mateja.marjanovic@rt-rk.com>
2019-05-26target/mips: Make the results of DIV_<U|S>.<B|H|W|D> the same as on hardwareMateja Marjanovic1-2/+3
MSA instructions DIV_<U|S>.<B|H|W|D> when dividing by zero, didn't return the same value when executed on a referent hardware (FPGA MIPS 64 r6, little endian) and when executed on QEMU, which is not a real bug, because the result when dividing by zero is UNPREDICTABLE [1] (page 141, 142). [1] MIPS Architecture for Programmers Volume IV-j: The MIPS64 SIMD Architecture Module, Revision 1.12 Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1554207110-9113-2-git-send-email-mateja.marjanovic@rt-rk.com>
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