riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-02-05	cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass	Claudio Fontana	1	-13/+23
2021-02-05	cpu: move do_unaligned_access to tcg_ops	Claudio Fontana	1	-1/+2
2021-02-05	cpu: move cc->transaction_failed to tcg_ops	Claudio Fontana	1	-1/+3
2021-02-05	cpu: move cc->do_interrupt to tcg_ops	Claudio Fontana	1	-2/+2
2021-02-05	cpu: Move tlb_fill to tcg_ops	Eduardo Habkost	1	-1/+1
2021-02-05	cpu: Move cpu_exec_* to tcg_ops	Eduardo Habkost	1	-1/+1
2021-02-05	cpu: Move synchronize_from_tb() to tcg_ops	Eduardo Habkost	1	-1/+3
2021-02-05	cpu: Introduce TCGCpuOperations struct	Eduardo Habkost	1	-1/+1
2021-01-14	target/mips: Remove vendor specific CPU definitions	Philippe Mathieu-Daudé	2	-10/+7
2021-01-14	target/mips: Remove CPU_NANOMIPS32 definition	Philippe Mathieu-Daudé	2	-5/+2
2021-01-14	target/mips: Remove CPU_R5900 definition	Philippe Mathieu-Daudé	1	-1/+0
2021-01-14	target/mips: Convert Rel6 LL/SC opcodes to decodetree	Philippe Mathieu-Daudé	2	-2/+2
2021-01-14	target/mips: Convert Rel6 LLD/SCD opcodes to decodetree	Philippe Mathieu-Daudé	2	-2/+3
2021-01-14	target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree	Philippe Mathieu-Daudé	2	-4/+8
2021-01-14	target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree	Philippe Mathieu-Daudé	2	-4/+5
2021-01-14	target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree	Philippe Mathieu-Daudé	2	-4/+6
2021-01-14	target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree	Philippe Mathieu-Daudé	2	-2/+3
2021-01-14	target/mips: Convert Rel6 COP1X opcode to decodetree	Philippe Mathieu-Daudé	2	-1/+2
2021-01-14	target/mips: Convert Rel6 Special2 opcode to decodetree	Philippe Mathieu-Daudé	3	-2/+9
2021-01-14	target/mips: Remove now unreachable LSA/DLSA opcodes code	Philippe Mathieu-Daudé	1	-23/+5
2021-01-14	target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes	Philippe Mathieu-Daudé	6	-0/+80
2021-01-14	target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes	Philippe Mathieu-Daudé	4	-0/+37
2021-01-14	target/mips: Extract LSA/DLSA translation generators	Philippe Mathieu-Daudé	4	-32/+71
2021-01-14	target/mips: Use decode_ase_msa() generated from decodetree	Philippe Mathieu-Daudé	3	-62/+11
2021-01-14	target/mips: Introduce decode tree bindings for MSA ASE	Philippe Mathieu-Daudé	4	-0/+68
2021-01-14	target/mips: Pass TCGCond argument to MSA gen_check_zero_element()	Philippe Mathieu-Daudé	1	-6/+4
2021-01-14	target/mips: Extract MSA translation routines	Philippe Mathieu-Daudé	3	-2249/+2266
2021-01-14	target/mips: Declare gen_msa/_branch() in 'translate.h'	Philippe Mathieu-Daudé	2	-2/+4
2021-01-14	target/mips: Extract MSA helper definitions	Philippe Mathieu-Daudé	2	-434/+445
2021-01-14	target/mips: Extract MSA helpers from op_helper.c	Philippe Mathieu-Daudé	2	-394/+393
2021-01-14	target/mips: Move msa_reset() to msa_helper.c	Philippe Mathieu-Daudé	4	-36/+39
2021-01-14	target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()	Philippe Mathieu-Daudé	1	-21/+48
2021-01-14	target/mips: Remove CPUMIPSState* argument from gen_msa*() methods	Philippe Mathieu-Daudé	1	-29/+28
2021-01-14	target/mips: Extract msa_translate_init() from mips_tcg_init()	Philippe Mathieu-Daudé	2	-13/+21
2021-01-14	target/mips: Alias MSA vector registers on FPU scalar registers	Philippe Mathieu-Daudé	1	-5/+9
2021-01-14	target/mips: Remove now unused ASE_MSA definition	Philippe Mathieu-Daudé	2	-5/+4
2021-01-14	target/mips: Simplify MSA TCG logic	Philippe Mathieu-Daudé	1	-12/+11
2021-01-14	target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA	Philippe Mathieu-Daudé	1	-1/+1
2021-01-14	target/mips: Simplify msa_reset()	Philippe Mathieu-Daudé	2	-4/+5
2021-01-14	target/mips: Introduce ase_msa_available() helper	Philippe Mathieu-Daudé	4	-11/+15
2021-01-14	target/mips/translate: Expose check_mips_64() to 32-bit mode	Philippe Mathieu-Daudé	2	-7/+3
2021-01-14	target/mips/translate: Extract decode_opc_legacy() from decode_opc()	Philippe Mathieu-Daudé	1	-20/+29
2021-01-14	target/mips: Only build TCG code when CONFIG_TCG is set	Philippe Mathieu-Daudé	1	-2/+6
2021-01-14	target/mips: Extract FPU specific definitions to translate.h	Philippe Mathieu-Daudé	2	-70/+71
2021-01-14	target/mips: Declare generic FPU / Coprocessor functions in translate.h	Philippe Mathieu-Daudé	2	-12/+24
2021-01-14	target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_instruction	Philippe Mathieu-Daudé	2	-362/+368
2021-01-14	target/mips: Replace gen_exception_err(err=0) by gen_exception_end()	Philippe Mathieu-Daudé	1	-3/+3
2021-01-14	target/mips/translate: Add declarations for generic code	Philippe Mathieu-Daudé	2	-38/+57
2021-01-14	target/mips/translate: Extract DisasContext structure	Philippe Mathieu-Daudé	2	-37/+51
2021-01-14	target/mips: Rename translate_init.c as cpu-defs.c	Philippe Mathieu-Daudé	2	-1/+1