riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-11-02	target/mips: Adjust style in msa_translate_init()	Philippe Mathieu-Daudé	1	-1/+3
2021-11-02	target/mips: Fix MSA MSUBV.B opcode	Philippe Mathieu-Daudé	1	-16/+16
2021-11-02	target/mips: Fix MSA MADDV.B opcode	Philippe Mathieu-Daudé	1	-16/+16
2021-11-02	target/mips: Make mips_cpu_tlb_fill sysemu only	Richard Henderson	5	-69/+5
2021-10-18	target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn()	Philippe Mathieu-Daudé	1	-4/+0
2021-10-18	target/mips: Fix DEXTRV_S.H DSP opcode	Philippe Mathieu-Daudé	1	-2/+1
2021-10-18	target/mips: Use tcg_constant_tl() in gen_compute_compact_branch()	Philippe Mathieu-Daudé	1	-3/+1
2021-10-18	target/mips: Use explicit extract32() calls in gen_msa_i5()	Philippe Mathieu-Daudé	1	-7/+4
2021-10-18	target/mips: Use tcg_constant_i32() in gen_msa_3rf()	Philippe Mathieu-Daudé	1	-9/+14
2021-10-18	target/mips: Use tcg_constant_i32() in gen_msa_2r()	Philippe Mathieu-Daudé	1	-3/+2
2021-10-18	target/mips: Use tcg_constant_i32() in gen_msa_2rf()	Philippe Mathieu-Daudé	1	-2/+1
2021-10-18	target/mips: Use tcg_constant_i32() in gen_msa_elm_df()	Philippe Mathieu-Daudé	1	-2/+1
2021-10-18	target/mips: Remove unused register from MSA 2R/2RF instruction format	Philippe Mathieu-Daudé	1	-6/+0
2021-10-17	target/mips: Check nanoMIPS DSP MULT[U] accumulator with Release 6	Philippe Mathieu-Daudé	1	-0/+6
2021-10-15	target/mips: Drop exit checks for singlestep_enabled	Richard Henderson	1	-32/+18
2021-10-15	target/mips: Fix single stepping	Richard Henderson	1	-9/+16
2021-10-13	target/mips: Use 8-byte memory ops for msa load/store	Richard Henderson	1	-130/+71
2021-10-13	target/mips: Use cpu_*_data_ra for msa load/store	Richard Henderson	1	-285/+135
2021-10-05	tcg: Rename TCGMemOpIdx to MemOpIdx	Richard Henderson	1	-3/+3
2021-09-21	hw/core: Make do_unaligned_access noreturn	Richard Henderson	1	-2/+2
2021-09-21	include/exec: Move cpu_signal_handler declaration	Richard Henderson	2	-5/+0
2021-09-14	target/mips: Restrict cpu_exec_interrupt() handler to sysemu	Philippe Mathieu-Daudé	5	-26/+22
2021-09-14	accel/tcg: Add DisasContextBase argument to translator_ld*	Ilya Leoshkevich	4	-9/+9
2021-08-25	target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian()	Philippe Mathieu-Daudé	3	-45/+50
2021-08-25	target/mips: Store CP0_Config0 in DisasContext	Philippe Mathieu-Daudé	2	-0/+2
2021-08-25	target/mips: Replace GET_LMASK64() macro by get_lmask(64) function	Philippe Mathieu-Daudé	1	-19/+16
2021-08-25	target/mips: Replace GET_LMASK() macro by get_lmask(32) function	Philippe Mathieu-Daudé	1	-11/+21
2021-08-25	target/mips: Call cpu_is_bigendian & inline GET_OFFSET in ld/st helpers	Philippe Mathieu-Daudé	1	-22/+33
2021-08-25	target/mips: Define gen_helper() macros in translate.h	Philippe Mathieu-Daudé	2	-12/+12
2021-08-25	target/mips: Use tcg_constant_i32() in generate_exception_err()	Philippe Mathieu-Daudé	1	-5/+2
2021-08-25	target/mips: Inline gen_helper_0e0i()	Philippe Mathieu-Daudé	1	-6/+2
2021-08-25	target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macros	Philippe Mathieu-Daudé	1	-5/+1
2021-08-25	target/mips: Simplify gen_helper() macros by using tcg_constant_i32()	Philippe Mathieu-Daudé	1	-15/+5
2021-08-25	target/mips: Use tcg_constant_i32() in gen_helper_0e2i()	Philippe Mathieu-Daudé	1	-12/+2
2021-08-25	target/mips: Remove gen_helper_1e2i()	Philippe Mathieu-Daudé	1	-6/+0
2021-08-25	target/mips: Remove gen_helper_0e3i()	Philippe Mathieu-Daudé	1	-6/+0
2021-08-25	target/mips: Remove duplicated check_cp1_enabled() calls in Loongson EXT	Philippe Mathieu-Daudé	1	-2/+0
2021-08-25	target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr	Philippe Mathieu-Daudé	1	-1/+1
2021-08-25	target/mips: Document Loongson-3A CPU definitions	Philippe Mathieu-Daudé	1	-2/+2
2021-08-25	target/mips: Convert Vr54xx MSA* opcodes to decodetree	Philippe Mathieu-Daudé	3	-53/+14
2021-08-25	target/mips: Convert Vr54xx MUL* opcodes to decodetree	Philippe Mathieu-Daudé	3	-24/+18
2021-08-25	target/mips: Convert Vr54xx MACC* opcodes to decodetree	Philippe Mathieu-Daudé	3	-16/+42
2021-08-25	target/mips: Introduce decodetree structure for NEC Vr54xx extension	Philippe Mathieu-Daudé	5	-0/+33
2021-08-25	target/mips: Extract NEC Vr54xx helpers to vr54xx_helper.c	Philippe Mathieu-Daudé	3	-118/+143
2021-08-25	target/mips: Extract NEC Vr54xx helper definitions	Philippe Mathieu-Daudé	2	-15/+27
2021-08-25	target/mips: Introduce generic TRANS() macro for decodetree helpers	Philippe Mathieu-Daudé	1	-0/+8
2021-08-25	target/mips: Rename 'rtype' as 'r'	Philippe Mathieu-Daudé	6	-46/+46
2021-08-25	target/mips: Merge 32-bit/64-bit Release6 decodetree definitions	Philippe Mathieu-Daudé	4	-40/+19
2021-08-25	target/mips: Decode vendor extensions before MIPS ISAs	Philippe Mathieu-Daudé	1	-3/+5
2021-08-25	target/mips: Simplify PREF opcode	Philippe Mathieu-Daudé	1	-6/+2