riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-04-26	target/mips: Remove stale TODO file	Thomas Huth	1	-51/+0
2022-04-21	compiler.h: replace QEMU_NORETURN with G_NORETURN	Marc-André Lureau	1	-8/+9
2022-04-20	exec/translator: Pass the locked filepointer to disas_log hook	Richard Henderson	1	-3/+4
2022-04-06	Remove qemu-common.h include from most units	Marc-André Lureau	1	-1/+0
2022-04-06	Replace TARGET_WORDS_BIGENDIAN	Marc-André Lureau	2	-7/+7
2022-04-06	Replace config-time define HOST_WORDS_BIGENDIAN	Marc-André Lureau	3	-29/+29
2022-03-29	target/mips: Fix address space range declaration on n32	WANG Xuerui	1	-1/+1
2022-03-09	Merge remote-tracking branch 'remotes/philmd/tags/mips-20220308' into staging	Peter Maydell	3	-19/+10
2022-03-07	target/mips: Remove duplicated MIPSCPU::cp0_count_rate	Philippe Mathieu-Daudé	3	-19/+9
2022-03-07	target/mips: Fix cycle counter timing calculations	Simon Burge	1	-1/+2
2022-03-06	target: Use ArchCPU as interface to target CPU	Philippe Mathieu-Daudé	1	-1/+1
2022-03-06	target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro	Philippe Mathieu-Daudé	2	-4/+1
2022-03-06	target: Use CPUArchState as interface to target-specific CPU state	Philippe Mathieu-Daudé	1	-4/+2
2022-03-06	target: Use forward declared type instead of structure type	Philippe Mathieu-Daudé	1	-7/+7
2022-03-06	target: Include missing 'cpu.h'	Philippe Mathieu-Daudé	1	-0/+1
2022-02-21	exec/exec-all: Move 'qemu/log.h' include in units requiring it	Philippe Mathieu-Daudé	3	-0/+3
2022-01-11	target/mips: Extract trap code into env->error_code	Richard Henderson	3	-8/+24
2022-01-11	target/mips: Extract break code into env->error_code	Richard Henderson	4	-5/+16
2022-01-08	exec/memop: Adding signedness to quad definitions	Frédéric Pétrot	3	-38/+38
2021-11-02	Merge remote-tracking branch 'remotes/philmd/tags/mips-20211102' into staging	Richard Henderson	4	-2087/+845
2021-11-02	target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU	Philippe Mathieu-Daudé	1	-1/+0
2021-11-02	target/mips: Fix Loongson-3A4000 MSAIR config register	Philippe Mathieu-Daudé	1	-0/+1
2021-11-02	target/mips: Remove one MSA unnecessary decodetree overlap group	Philippe Mathieu-Daudé	1	-182/+180
2021-11-02	target/mips: Remove generic MSA opcode	Philippe Mathieu-Daudé	2	-9/+0
2021-11-02	target/mips: Convert CTCMSA opcode to decodetree	Philippe Mathieu-Daudé	2	-58/+16
2021-11-02	target/mips: Convert CFCMSA opcode to decodetree	Philippe Mathieu-Daudé	2	-9/+23
2021-11-02	target/mips: Convert MSA MOVE.V opcode to decodetree	Philippe Mathieu-Daudé	2	-6/+20
2021-11-02	target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree	Philippe Mathieu-Daudé	2	-88/+19
2021-11-02	target/mips: Convert MSA COPY_U opcode to decodetree	Philippe Mathieu-Daudé	2	-26/+41
2021-11-02	target/mips: Convert MSA ELM instruction format to decodetree	Philippe Mathieu-Daudé	2	-13/+52
2021-11-02	target/mips: Convert MSA 3R instruction format to decodetree (part 4/4)	Philippe Mathieu-Daudé	2	-863/+106
2021-11-02	target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)	Philippe Mathieu-Daudé	2	-34/+9
2021-11-02	target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)	Philippe Mathieu-Daudé	2	-158/+35
2021-11-02	target/mips: Convert MSA 3R instruction format to decodetree (part 1/4)	Philippe Mathieu-Daudé	2	-12/+11
2021-11-02	target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD)	Philippe Mathieu-Daudé	2	-176/+76
2021-11-02	target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF)	Philippe Mathieu-Daudé	2	-39/+38
2021-11-02	target/mips: Convert MSA VEC instruction format to decodetree	Philippe Mathieu-Daudé	2	-75/+31
2021-11-02	target/mips: Convert MSA 2R instruction format to decodetree	Philippe Mathieu-Daudé	2	-75/+19
2021-11-02	target/mips: Convert MSA FILL opcode to decodetree	Philippe Mathieu-Daudé	2	-12/+21
2021-11-02	target/mips: Convert MSA 2RF instruction format to decodetree	Philippe Mathieu-Daudé	2	-85/+53
2021-11-02	target/mips: Convert MSA load/store instruction format to decodetree	Philippe Mathieu-Daudé	2	-59/+36
2021-11-02	target/mips: Convert MSA I8 instruction format to decodetree	Philippe Mathieu-Daudé	2	-56/+27
2021-11-02	target/mips: Convert MSA SHF opcode to decodetree	Philippe Mathieu-Daudé	2	-17/+22
2021-11-02	target/mips: Convert MSA BIT instruction format to decodetree	Philippe Mathieu-Daudé	2	-97/+101
2021-11-02	target/mips: Convert MSA I5 instruction format to decodetree	Philippe Mathieu-Daudé	2	-77/+41
2021-11-02	target/mips: Convert MSA LDI opcode to decodetree	Philippe Mathieu-Daudé	2	-9/+21
2021-11-02	target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v	Philippe Mathieu-Daudé	2	-18/+17
2021-11-02	target/mips: Use enum definitions from CPUMIPSMSADataFormat enum	Philippe Mathieu-Daudé	1	-3/+3
2021-11-02	target/mips: Have check_msa_access() return a boolean	Philippe Mathieu-Daudé	1	-7/+18
2021-11-02	target/mips: Use dup_const() to simplify	Philippe Mathieu-Daudé	1	-20/+3