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AgeCommit message (Expand)AuthorFilesLines
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova1-3/+2
2017-07-17target/mips: optimize WSBH, DSBH and DSHDAurelien Jarno1-6/+12
2017-07-17mips: set CP0 Debug DExcCode for SDBBP instructionPavel Dovgalyuk1-0/+2
2017-07-11target/mips: fix msa copy_[s|u]_df rd = 0 corner caseMiodrag Dinic1-2/+6
2017-07-04vcpu_dirty: share the same field in CPUState for all acceleratorsSergio Andres Gomez Del Real1-2/+2
2017-06-05target/mips: optimize indirect branchesAurelien Jarno1-1/+1
2017-06-05target/mips: optimize cross-page direct jumps in softmmuAurelien Jarno1-1/+1
2017-03-20target/mips: fix delay slot detection in gen_msa_branch()Yongbok Kim1-1/+1
2017-03-20target-mips: replace few LOG_DISAS() with trace pointsPhilippe Mathieu-Daudé2-14/+16
2017-03-20target-mips: replace break by goto cp0_unimplementedPhilippe Mathieu-Daudé1-44/+44
2017-03-20target-mips: log bad coprocessor0 register accesses with LOG_UNIMPPhilippe Mathieu-Daudé1-6/+6
2017-03-20target-mips: remove old & unuseful commentsPhilippe Mathieu-Daudé1-4/+0
2017-03-20target-mips: fix compiler warnings (clang 5)Philippe Mathieu-Daudé1-4/+12
2017-03-09target/mips: hold BQL for timer interruptsYongbok Kim1-3/+18
2017-03-03KVM: do not use sigtimedwait to catch SIGBUSPaolo Bonzini1-6/+0
2017-03-03KVM: remove kvm_arch_on_sigbusPaolo Bonzini1-6/+0
2017-02-21target-mips: Provide function to test if a CPU supports an ISAPaul Burton2-0/+11
2017-01-24migration: extend VMStateInfoJianjun Duan1-4/+10
2017-01-20Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell1-0/+5
2017-01-16stubs: remove stubs/kvm.cPaolo Bonzini1-0/+5
2017-01-13cputlb: drop flush_global flag from tlb_flushAlex Bennée3-8/+8
2017-01-13qom/cpu: move tlb_flush to cpu_common_resetAlex Bennée2-2/+4
2017-01-10target-mips: Use clz opcodeRichard Henderson3-36/+16
2017-01-10target-mips: Use the new extract opRichard Henderson1-7/+5
2016-12-20Move target-* CPU file into a target/ folderThomas Huth19-0/+38839