riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-02-21	target/mips: Use GPR move functions in gen_HILO1_tx79()	Philippe Mathieu-Daudé	1	-17/+4
2021-02-21	target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers	Philippe Mathieu-Daudé	2	-0/+22
2021-02-21	target/mips: Rename 128-bit upper halve GPR registers	Philippe Mathieu-Daudé	1	-1/+3
2021-02-21	target/mips: Promote 128-bit multimedia registers as global ones	Philippe Mathieu-Daudé	3	-27/+34
2021-02-21	target/mips: Make cpu_HI/LO registers public	Philippe Mathieu-Daudé	2	-1/+2
2021-02-21	target/mips: Include missing "tcg/tcg.h" header	Philippe Mathieu-Daudé	1	-0/+1
2021-02-21	target/mips: Remove unused 'rw' argument from page_table_walk_refill()	Philippe Mathieu-Daudé	1	-3/+3
2021-02-21	target/mips: Let CPUMIPSTLBContext::map_address() take MMUAccessType	Philippe Mathieu-Daudé	2	-10/+10
2021-02-21	target/mips: Let get_seg*_physical_address() take MMUAccessType arg	Philippe Mathieu-Daudé	1	-5/+6
2021-02-21	target/mips: Let get_physical_address() take MMUAccessType argument	Philippe Mathieu-Daudé	1	-10/+10
2021-02-21	target/mips: Let raise_mmu_exception() take MMUAccessType argument	Philippe Mathieu-Daudé	1	-5/+5
2021-02-21	target/mips: Let cpu_mips_translate_address() take MMUAccessType arg	Philippe Mathieu-Daudé	2	-4/+4
2021-02-21	target/mips: Let do_translate_address() take MMUAccessType argument	Philippe Mathieu-Daudé	1	-3/+4
2021-02-21	target/mips: Replace magic value by MMU_DATA_LOAD definition	Philippe Mathieu-Daudé	2	-2/+2
2021-02-21	target/mips: Remove unused MMU definitions	Philippe Mathieu-Daudé	1	-16/+0
2021-02-21	target/mips: Remove access_type argument from get_physical_address()	Philippe Mathieu-Daudé	1	-13/+9
2021-02-21	target/mips: Remove access_type arg from get_segctl_physical_address()	Philippe Mathieu-Daudé	1	-10/+10
2021-02-21	target/mips: Remove access_type argument from get_seg_physical_address	Philippe Mathieu-Daudé	1	-3/+3
2021-02-21	target/mips: Remove access_type argument from map_address() handler	Philippe Mathieu-Daudé	2	-12/+11
2021-02-21	target/mips: fetch code with translator_ld	Philippe Mathieu-Daudé	1	-10/+10
2021-02-18	target/mips: Create mips_io_recompile_replay_branch	Richard Henderson	1	-0/+18
2021-02-16	sev/i386: Don't allow a system reset under an SEV-ES guest	Tom Lendacky	1	-0/+5
2021-02-05	cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass	Claudio Fontana	1	-13/+23
2021-02-05	cpu: move do_unaligned_access to tcg_ops	Claudio Fontana	1	-1/+2
2021-02-05	cpu: move cc->transaction_failed to tcg_ops	Claudio Fontana	1	-1/+3
2021-02-05	cpu: move cc->do_interrupt to tcg_ops	Claudio Fontana	1	-2/+2
2021-02-05	cpu: Move tlb_fill to tcg_ops	Eduardo Habkost	1	-1/+1
2021-02-05	cpu: Move cpu_exec_* to tcg_ops	Eduardo Habkost	1	-1/+1
2021-02-05	cpu: Move synchronize_from_tb() to tcg_ops	Eduardo Habkost	1	-1/+3
2021-02-05	cpu: Introduce TCGCpuOperations struct	Eduardo Habkost	1	-1/+1
2021-01-14	target/mips: Remove vendor specific CPU definitions	Philippe Mathieu-Daudé	2	-10/+7
2021-01-14	target/mips: Remove CPU_NANOMIPS32 definition	Philippe Mathieu-Daudé	2	-5/+2
2021-01-14	target/mips: Remove CPU_R5900 definition	Philippe Mathieu-Daudé	1	-1/+0
2021-01-14	target/mips: Convert Rel6 LL/SC opcodes to decodetree	Philippe Mathieu-Daudé	2	-2/+2
2021-01-14	target/mips: Convert Rel6 LLD/SCD opcodes to decodetree	Philippe Mathieu-Daudé	2	-2/+3
2021-01-14	target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree	Philippe Mathieu-Daudé	2	-4/+8
2021-01-14	target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree	Philippe Mathieu-Daudé	2	-4/+5
2021-01-14	target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree	Philippe Mathieu-Daudé	2	-4/+6
2021-01-14	target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree	Philippe Mathieu-Daudé	2	-2/+3
2021-01-14	target/mips: Convert Rel6 COP1X opcode to decodetree	Philippe Mathieu-Daudé	2	-1/+2
2021-01-14	target/mips: Convert Rel6 Special2 opcode to decodetree	Philippe Mathieu-Daudé	3	-2/+9
2021-01-14	target/mips: Remove now unreachable LSA/DLSA opcodes code	Philippe Mathieu-Daudé	1	-23/+5
2021-01-14	target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes	Philippe Mathieu-Daudé	6	-0/+80
2021-01-14	target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes	Philippe Mathieu-Daudé	4	-0/+37
2021-01-14	target/mips: Extract LSA/DLSA translation generators	Philippe Mathieu-Daudé	4	-32/+71
2021-01-14	target/mips: Use decode_ase_msa() generated from decodetree	Philippe Mathieu-Daudé	3	-62/+11
2021-01-14	target/mips: Introduce decode tree bindings for MSA ASE	Philippe Mathieu-Daudé	4	-0/+68
2021-01-14	target/mips: Pass TCGCond argument to MSA gen_check_zero_element()	Philippe Mathieu-Daudé	1	-6/+4
2021-01-14	target/mips: Extract MSA translation routines	Philippe Mathieu-Daudé	3	-2249/+2266
2021-01-14	target/mips: Declare gen_msa/_branch() in 'translate.h'	Philippe Mathieu-Daudé	2	-2/+4