| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2017-03-20 | target/mips: fix delay slot detection in gen_msa_branch() | Yongbok Kim | 1 | -1/+1 |
| 2017-03-20 | target-mips: replace few LOG_DISAS() with trace points | Philippe Mathieu-Daudé | 1 | -14/+11 |
| 2017-03-20 | target-mips: replace break by goto cp0_unimplemented | Philippe Mathieu-Daudé | 1 | -44/+44 |
| 2017-03-20 | target-mips: log bad coprocessor0 register accesses with LOG_UNIMP | Philippe Mathieu-Daudé | 1 | -6/+6 |
| 2017-03-20 | target-mips: remove old & unuseful comments | Philippe Mathieu-Daudé | 1 | -4/+0 |
| 2017-02-21 | target-mips: Provide function to test if a CPU supports an ISA | Paul Burton | 1 | -0/+10 |
| 2017-01-10 | target-mips: Use clz opcode | Richard Henderson | 1 | -7/+16 |
| 2017-01-10 | target-mips: Use the new extract op | Richard Henderson | 1 | -7/+5 |
| 2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth | 1 | -0/+20423 |
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index : riscv-gnu-toolchain/qemu.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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