riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-04-13	target/mips: Fix TCG temporary leak in gen_cache_operation()	Philippe Mathieu-Daudé	1	-0/+2
2021-03-13	target/mips/tx79: Salvage instructions description comment	Philippe Mathieu-Daudé	1	-160/+0
2021-03-13	target/mips: Remove 'C790 Multimedia Instructions' dead code	Philippe Mathieu-Daudé	1	-371/+0
2021-03-13	target/mips/tx79: Move PCPYLD / PCPYUD opcodes to decodetree	Philippe Mathieu-Daudé	1	-80/+0
2021-03-13	target/mips/tx79: Move PCPYH opcode to decodetree	Philippe Mathieu-Daudé	1	-39/+0
2021-03-13	target/mips/translate: Simplify PCPYH using deposit_i64()	Philippe Mathieu-Daudé	1	-30/+4
2021-03-13	target/mips/translate: Make gen_rdhwr() public	Philippe Mathieu-Daudé	1	-1/+1
2021-03-13	target/mips/tx79: Move MTHI1 / MTLO1 opcodes to decodetree	Philippe Mathieu-Daudé	1	-25/+0
2021-03-13	target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree	Philippe Mathieu-Daudé	1	-12/+3
2021-03-13	target/mips: Use gen_load_gpr[_hi]() when possible	Philippe Mathieu-Daudé	1	-23/+6
2021-03-13	target/mips: Extract MXU code to new mxu_translate.c file	Philippe Mathieu-Daudé	1	-1605/+0
2021-03-13	target/mips: Introduce mxu_translate_init() helper	Philippe Mathieu-Daudé	1	-12/+16
2021-03-13	target/mips: Simplify decode_opc_mxu() ifdef'ry	Philippe Mathieu-Daudé	1	-4/+2
2021-03-13	target/mips: Convert decode_ase_mxu() to decodetree prototype	Philippe Mathieu-Daudé	1	-3/+5
2021-03-13	target/mips: Rename decode_opc_mxu() as decode_ase_mxu()	Philippe Mathieu-Daudé	1	-2/+2
2021-03-13	target/mips: Move MUL opcode check from decode_mxu() to decode_legacy()	Philippe Mathieu-Daudé	1	-14/+5
2021-03-13	target/mips: Use OPC_MUL instead of OPC__MXU_MUL	Philippe Mathieu-Daudé	1	-2/+1
2021-03-13	target/mips: Pass instruction opcode to decode_opc_mxu()	Philippe Mathieu-Daudé	1	-7/+7
2021-03-13	target/mips: Remove unused CPUMIPSState* from MXU functions	Philippe Mathieu-Daudé	1	-10/+10
2021-03-13	target/mips: Remove XBurst Media eXtension Unit dead code	Philippe Mathieu-Daudé	1	-1286/+0
2021-03-13	target/mips: Rewrite complex ifdef'ry	Philippe Mathieu-Daudé	1	-4/+7
2021-03-10	semihosting: Move include/hw/semihosting/ -> include/semihosting/	Philippe Mathieu-Daudé	1	-1/+1
2021-02-21	target/mips: Use GPR move functions in gen_HILO1_tx79()	Philippe Mathieu-Daudé	1	-17/+4
2021-02-21	target/mips: Introduce gen_load_gpr_hi() / gen_store_gpr_hi() helpers	Philippe Mathieu-Daudé	1	-0/+18
2021-02-21	target/mips: Rename 128-bit upper halve GPR registers	Philippe Mathieu-Daudé	1	-1/+3
2021-02-21	target/mips: Promote 128-bit multimedia registers as global ones	Philippe Mathieu-Daudé	1	-24/+24
2021-02-21	target/mips: Make cpu_HI/LO registers public	Philippe Mathieu-Daudé	1	-1/+1
2021-02-21	target/mips: fetch code with translator_ld	Philippe Mathieu-Daudé	1	-10/+10
2021-01-14	target/mips: Convert Rel6 LL/SC opcodes to decodetree	Philippe Mathieu-Daudé	1	-2/+0
2021-01-14	target/mips: Convert Rel6 LLD/SCD opcodes to decodetree	Philippe Mathieu-Daudé	1	-2/+0
2021-01-14	target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree	Philippe Mathieu-Daudé	1	-4/+1
2021-01-14	target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree	Philippe Mathieu-Daudé	1	-4/+0
2021-01-14	target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree	Philippe Mathieu-Daudé	1	-4/+1
2021-01-14	target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree	Philippe Mathieu-Daudé	1	-2/+0
2021-01-14	target/mips: Convert Rel6 COP1X opcode to decodetree	Philippe Mathieu-Daudé	1	-1/+0
2021-01-14	target/mips: Convert Rel6 Special2 opcode to decodetree	Philippe Mathieu-Daudé	1	-2/+0
2021-01-14	target/mips: Remove now unreachable LSA/DLSA opcodes code	Philippe Mathieu-Daudé	1	-23/+5
2021-01-14	target/mips: Introduce decodetree helpers for Release6 LSA/DLSA opcodes	Philippe Mathieu-Daudé	1	-0/+5
2021-01-14	target/mips: Extract LSA/DLSA translation generators	Philippe Mathieu-Daudé	1	-32/+4
2021-01-14	target/mips: Use decode_ase_msa() generated from decodetree	Philippe Mathieu-Daudé	1	-22/+10
2021-01-14	target/mips: Extract MSA translation routines	Philippe Mathieu-Daudé	1	-2249/+0
2021-01-14	target/mips: Declare gen_msa/_branch() in 'translate.h'	Philippe Mathieu-Daudé	1	-2/+2
2021-01-14	target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ()	Philippe Mathieu-Daudé	1	-21/+48
2021-01-14	target/mips: Remove CPUMIPSState* argument from gen_msa*() methods	Philippe Mathieu-Daudé	1	-29/+28
2021-01-14	target/mips: Extract msa_translate_init() from mips_tcg_init()	Philippe Mathieu-Daudé	1	-13/+18
2021-01-14	target/mips: Alias MSA vector registers on FPU scalar registers	Philippe Mathieu-Daudé	1	-5/+9
2021-01-14	target/mips: Simplify MSA TCG logic	Philippe Mathieu-Daudé	1	-12/+11
2021-01-14	target/mips: Introduce ase_msa_available() helper	Philippe Mathieu-Daudé	1	-4/+2
2021-01-14	target/mips/translate: Expose check_mips_64() to 32-bit mode	Philippe Mathieu-Daudé	1	-5/+3
2021-01-14	target/mips/translate: Extract decode_opc_legacy() from decode_opc()	Philippe Mathieu-Daudé	1	-20/+29