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2023-07-10target/mips/mxu: Add S32MADD/MADDU/MSUB/MSUBU instructionsSiarhei Volkau1-5/+2
These instructions used to multiply 2x32-bit GPR sources & accumulate result into 64-bit pair of XRF registers. These instructions stain HI/LO registers with the final result. Their opcode is close to the MIPS32R1 MADD[U]/MSUB[U], so it have to call decode_opc_special2_legacy when failing to find MXU opcode. Moreover, it solves issue with reinventing MUL and malfunction MULU/CLZ/CLO instructions. Signed-off-by: Siarhei Volkau <lis8215@gmail.com> Message-Id: <20230608104222.1520143-5-lis8215@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-07-10target/mips: Implement Loongson CSR instructionsJiaxun Yang1-0/+3
Loongson introduced CSR instructions since 3A4000, which looks similar to IOCSR and CPUCFG instructions we seen in LoongArch. Unfortunately we don't have much document about those instructions, bit fields of CPUCFG instructions and IOCSR registers can be found at 3A4000's user manual, while instruction encodings can be found at arch/mips/include/asm/mach-loongson64/loongson_regs.h from Linux Kernel. Our predefined CPUCFG bits are differ from actual 3A4000, since we can't emulate all CPUCFG features present in 3A4000 for now, we just enable bits for what we have in TCG. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20230521214832.20145-2-jiaxun.yang@flygoat.com> [JY: Fixed typo in ase_lcsr_available(), retrict GEN_FALSE_TRANS] [PMD: Fix meson's mips_softmmu_ss -> mips_system_ss, restrict AddressSpace/MemoryRegion to SysEmu] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-06-05target/*: Add missing includes of exec/translation-block.hRichard Henderson1-0/+1
This had been pulled in via exec/exec-all.h, via exec/translator.h, but the include of exec-all.h will be removed. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-05target/mips: Tidy helpers for translationRichard Henderson1-8/+2
Move most includes from *translate*.c to translate.h, ensuring that we get the ordering correct. Ensure cpu.h is first. Use disas/disas.h instead of exec/log.h. Drop otherwise unused includes. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-05accel/tcg: Introduce translator_io_startRichard Henderson1-19/+10
New wrapper around gen_io_start which takes care of the USE_ICOUNT check, as well as marking the DisasContext to end the TB. Remove exec/gen-icount.h. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-05tcg: Pass TCGHelperInfo to tcg_gen_callNRichard Henderson1-0/+5
In preparation for compiling tcg/ only once, eliminate the all_helpers array. Instantiate the info structs for the generic helpers in accel/tcg/, and the structs for the target-specific helpers in each translate.c. Since we don't see all of the info structs at startup, initialize at first use, using g_once_init_* to make sure we don't race while doing so. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-05target/mips: Finish conversion to tcg_gen_qemu_{ld,st}_*Richard Henderson1-4/+4
Convert away from the old interface with the implicit MemOp argument. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230502135741.1158035-6-richard.henderson@linaro.org>
2023-04-20target/mips: tcg: detect out-of-bounds accesses to cpu_gpr and cpu_gpr_hiPaolo Bonzini1-0/+4
In some cases (for example gen_compute_branch_nm in nanomips_translate.c.inc) registers can be unused on some paths and a negative value is passed in that case: gen_compute_branch_nm(ctx, OPC_BPOSGE32, 4, -1, -2, imm << 1); To avoid an out of bounds access in those cases, introduce assertions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-03-13target/mips: Avoid tcg_const_* throughoutRichard Henderson1-28/+28
All remaining uses are strictly read-only. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/mips: Avoid tcg_const_tl in gen_r6_ldRichard Henderson1-2/+2
Allocate a separate temp for modification. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/mips: Split out gen_lxrRichard Henderson1-76/+40
Common subroutine for LDR and LWR. Use tcg_constant_tl of ~1 instead of tcg_const_tl of 0x..fe. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/mips: Split out gen_lxlRichard Henderson1-70/+36
Common subroutine for LDL and LWL. Use tcg_constant_tl instead of tcg_const_tl and t2. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/mips: Drop tcg_temp_free from translate.cRichard Henderson1-523/+14
Translators are no longer required to free tcg temporaries. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-07target/mips: Fix JALS32/J32 instruction handling for microMIPSMarcin Nowakowski1-0/+8
microMIPS J & JAL instructions perform a jump in a 128MB region and 5 top bits of the address need to be preserved. This is different behavior compared to standard mips systems, where the jump is executed within a 256MB region. Note that microMIPS32 instruction set documentation appears to have inconsistent information regarding JALX32 instruction - it is written in the doc that: "To execute a procedure call within the current 256 MB-aligned region (...) The low 26 bits of the target address is the target field shifted left 2 bits." But the target address is already 26 bits. Moreover, the operation description indicates that 28 bits are copied, so the statement about use of 26 bits is _most likely_ incorrect and the corresponding code remains the same as for standard mips instruction set. Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230216051717.3911212-2-marcin.nowakowski@fungible.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-03-01target/mips: Don't use tcg_temp_local_newRichard Henderson1-43/+14
Since tcg_temp_new is now identical, use that. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-01accel/tcg: Pass max_insn to gen_intermediate_code by pointerRichard Henderson1-1/+1
In preparation for returning the number of insns generated via the same pointer. Adjust only the prototypes so far. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-02-08Drop duplicate #includeMarkus Armbruster1-1/+0
Tracked down with the help of scripts/clean-includes. Signed-off-by: Markus Armbruster <armbru@redhat.com> Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20230202133830.2152150-21-armbru@redhat.com>
2022-11-08target/mips: Don't check COP1X for 64 bit FP modeJiaxun Yang1-1/+1
Some implementations (i.e. Loongson-2F) may decide to implement a 64 bit FPU without implementing COP1X instructions. As the eligibility of 64 bit FP instructions is already determined by CP0St_FR, there is no need to check for COP1X again. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221102165719.190378-1-jiaxun.yang@flygoat.com> [PMD: Add missing trailing parenthesis (buildfix)] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-11-08target/mips: Enable LBX/LWX/* instructions for OcteonPavel Dovgalyuk1-4/+8
This patch changes condition and function name for enabling indexed load instructions for Octeon vCPUs. Octeons do not have DSP extension, but implement LBX-and-others. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <166728058455.229236.13834649461181619195.stgit@pasha-ThinkPad-X280> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-10-26target/mips: Convert to tcg_ops restore_state_to_opcRichard Henderson1-2/+6
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-09-13target/mips: Honour -semihosting-config userspace=onPeter Maydell1-4/+5
Honour the commandline -semihosting-config userspace=on option, instead of always permitting userspace semihosting calls in system emulation mode, by passing the correct value to the is_userspace argument of semihosting_enabled(). Note that this is a behaviour change: if the user wants to do semihosting calls from userspace they must now specifically enable them on the command line. MIPS semihosting is not implemented for linux-user builds. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220822141230.3658237-5-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-09-06accel/tcg: Add pc and host_pc params to gen_intermediate_codeRichard Henderson1-2/+3
Pass these along to translator_loop -- pc may be used instead of tb->pc, and host_pc is currently unused. Adjust all targets at one time. Acked-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Tested-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-08-02target/mips: Advance pc after semihosting exceptionRichard Henderson1-5/+5
Delay generating the exception until after we know the insn length, and record that length in env->error_code. Fixes: 8ec7e3c53d4 ("target/mips: Use an exception for semihosting") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1126 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-12target/mips: introduce decodetree structure for Cavium Octeon extensionPavel Dovgalyuk1-0/+5
This patch adds decodetree for Cavium Octeon extension and an instruction set extension flag for using it in CPU models. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <165572672162.167724.13656301229517693806.stgit@pasha-ThinkPad-X280> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-06-28target/mips: Use an exception for semihostingRichard Henderson1-10/+2
Within do_interrupt, we hold the iothread lock, which is required for Chardev access for the console, and for the round trip for use_gdb_syscalls(). Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-11target/mips: Fix handling of unaligned memory access for nanoMIPS ISADragan Mladjenovic1-2/+3
nanoMIPS ISA does not support unaligned memory access. Adjust DisasContext's default_tcg_memop_mask to reflect this. Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com> Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220504110403.613168-6-stefan.pejic@syrmia.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-04-20exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson1-3/+4
We have fetched and locked the logfile in translator_loop. Pass the filepointer down to the disas_log hook so that it need not be fetched and locked again. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220417183019.755276-13-richard.henderson@linaro.org>
2022-01-11target/mips: Extract trap code into env->error_codeRichard Henderson1-4/+20
Simplify cpu_loop by doing all of the decode in translate. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220107213243.212806-18-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-01-11target/mips: Extract break code into env->error_codeRichard Henderson1-1/+11
Simplify cpu_loop by doing all of the decode in translate. This fixes a bug in that cpu_loop was not handling the different layout of the R6 version of break16. This fixes a bug in that cpu_loop extracted the wrong bits for the mips16e break16 instruction. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220107213243.212806-17-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot1-29/+29
Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-18target/mips: Remove unused TCG temporary in gen_mipsdsp_accinsn()Philippe Mathieu-Daudé1-4/+0
Since gen_mipsdsp_accinsn() got added in commit b53371ed5d4 ("target-mips: Add ASE DSP accumulator instructions"), the 'v2_t' TCG temporary has never been used. Remove it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211014224551.2204949-1-f4bug@amsat.org>
2021-10-18target/mips: Fix DEXTRV_S.H DSP opcodePhilippe Mathieu-Daudé1-2/+1
While for the DEXTR_S.H opcode: "The shift argument is provided in the instruction." For the DEXTRV_S.H opcode we have: "The five least-significant bits of register rs provide the shift argument, interpreted as a five-bit unsigned integer; the remaining bits in rs are ignored." While 't1' contains the 'rs' register content (the shift value for DEXTR_S.H), we need to load the value of 'rs' for DEXTRV_S.H. We can directly use the v1_t TCG register which already contains this shift value. Fixes: b53371ed5d4 ("target-mips: Add ASE DSP accumulator instructions") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211013215652.1764551-1-f4bug@amsat.org>
2021-10-18target/mips: Use tcg_constant_tl() in gen_compute_compact_branch()Philippe Mathieu-Daudé1-3/+1
The offset is constant and read-only: move it to the constant pool. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20211003175743.3738710-9-f4bug@amsat.org>
2021-10-15target/mips: Drop exit checks for singlestep_enabledRichard Henderson1-32/+18
GDB single-stepping is now handled generically. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-15target/mips: Fix single steppingRichard Henderson1-9/+16
As per an ancient comment in mips_tr_translate_insn about the expectations of gdb, when restarting the insn in a delay slot we also re-execute the branch. Which means that we are expected to execute two insns in this case. This has been broken since 8b86d6d2580, where we forced max_insns to 1 while single-stepping. This resulted in an exit from the translator loop after the branch but before the delay slot is translated. Increase the max_insns to 2 for this case. In addition, bypass the end-of-page check, for when the branch itself ends the page. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-14accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich1-4/+4
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> [rth: Split out of a larger patch.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-08-25target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian()Philippe Mathieu-Daudé1-35/+35
Add the inlined cpu_is_bigendian() function in "translate.h". Replace the TARGET_WORDS_BIGENDIAN #ifdef'ry by calls to cpu_is_bigendian(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210818164321.2474534-6-f4bug@amsat.org>
2021-08-25target/mips: Store CP0_Config0 in DisasContextPhilippe Mathieu-Daudé1-0/+1
Most TCG helpers only have access to a DisasContext pointer, not CPUMIPSState. Store a copy of CPUMIPSState::CP0_Config0 in DisasContext so we can access it from TCG helpers. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210818164321.2474534-5-f4bug@amsat.org>
2021-08-25target/mips: Define gen_helper() macros in translate.hPhilippe Mathieu-Daudé1-12/+0
To be able to split some code calling the gen_helper() macros out of the huge translate.c, we need to define them in the 'translate.h' local header. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210816205107.2051495-9-f4bug@amsat.org>
2021-08-25target/mips: Use tcg_constant_i32() in generate_exception_err()Philippe Mathieu-Daudé1-5/+2
excp/err are temporaries input, so we can replace tcg_const_i32() calls by tcg_constant_i32() equivalent. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210816205107.2051495-8-f4bug@amsat.org>
2021-08-25target/mips: Inline gen_helper_0e0i()Philippe Mathieu-Daudé1-6/+2
gen_helper_0e0i() is one-line long and is only used twice: simply inline it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210816205107.2051495-7-f4bug@amsat.org>
2021-08-25target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macrosPhilippe Mathieu-Daudé1-5/+1
gen_helper_1e1i() is one-line long and is used in one place: simply inline it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210816205107.2051495-6-f4bug@amsat.org>
2021-08-25target/mips: Simplify gen_helper() macros by using tcg_constant_i32()Philippe Mathieu-Daudé1-15/+5
In all call sites the last argument is always used as a read-only value, so we can replace tcg_const_i32() temporary by tcg_constant_i32(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210816205107.2051495-5-f4bug@amsat.org>
2021-08-25target/mips: Use tcg_constant_i32() in gen_helper_0e2i()Philippe Mathieu-Daudé1-12/+2
$rt register is used read-only, so we can replace tcg_const_i32() temporary by tcg_constant_i32(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210816205107.2051495-4-f4bug@amsat.org>
2021-08-25target/mips: Remove gen_helper_1e2i()Philippe Mathieu-Daudé1-6/+0
gen_helper_1e2i() is unused since commit 33a07fa2db6 ("target/mips: reimplement SC instruction emulation and use cmpxchg"), remove it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210816205107.2051495-3-f4bug@amsat.org>
2021-08-25target/mips: Remove gen_helper_0e3i()Philippe Mathieu-Daudé1-6/+0
gen_helper_0e3i() is unused since commit 895c2d04359 ("target-mips: switch to AREG0 free mode"), remove it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210816205107.2051495-2-f4bug@amsat.org>
2021-08-25target/mips: Remove duplicated check_cp1_enabled() calls in Loongson EXTPhilippe Mathieu-Daudé1-2/+0
We already call check_cp1_enabled() earlier in the "pre-conditions" checks for GSLWXC1 and GSLDXC1 in gen_loongson_lsdc2() prologue. Remove the duplicated calls. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn> Message-Id: <20210816001031.1720432-1-f4bug@amsat.org>
2021-08-25target/mips: Convert Vr54xx MSA* opcodes to decodetreePhilippe Mathieu-Daudé1-53/+2
Convert the following Integer Multiply-Accumulate opcodes: * MSAC Multiply, negate, accumulate, and move LO * MSACHI Multiply, negate, accumulate, and move HI * MSACHIU Unsigned multiply, negate, accumulate, and move HI * MSACU Unsigned multiply, negate, accumulate, and move LO Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210808173018.90960-8-f4bug@amsat.org>
2021-08-25target/mips: Convert Vr54xx MUL* opcodes to decodetreePhilippe Mathieu-Daudé1-24/+0
Convert the following Integer Multiply-Accumulate opcodes: * MULHI Multiply and move HI * MULHIU Unsigned multiply and move HI * MULS Multiply, negate, and move LO * MULSHI Multiply, negate, and move HI * MULSHIU Unsigned multiply, negate, and move HI * MULSU Unsigned multiply, negate, and move LO Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210808173018.90960-7-f4bug@amsat.org>
2021-08-25target/mips: Convert Vr54xx MACC* opcodes to decodetreePhilippe Mathieu-Daudé1-16/+0
Convert the following Integer Multiply-Accumulate opcodes: * MACC Multiply, accumulate, and move LO * MACCHI Multiply, accumulate, and move HI * MACCHIU Unsigned multiply, accumulate, and move HI * MACCU Unsigned multiply, accumulate, and move LO Since all opcodes are generated using the same pattern, we add the gen_helper_mult_acc_t typedef and MULT_ACC() macro to remove boilerplate code. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210808173018.90960-6-f4bug@amsat.org>
generated by cgit v1.1 at 2025-01-15 16:04:39 +0000