riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-03-09	Merge remote-tracking branch 'remotes/philmd/tags/mips-20220308' into staging	Peter Maydell	1	-0/+9
2022-03-07	target/mips: Remove duplicated MIPSCPU::cp0_count_rate	Philippe Mathieu-Daudé	1	-0/+9
2022-03-06	target: Use forward declared type instead of structure type	Philippe Mathieu-Daudé	1	-7/+7
2022-03-06	target: Include missing 'cpu.h'	Philippe Mathieu-Daudé	1	-0/+1
2021-09-21	include/exec: Move cpu_signal_handler declaration	Richard Henderson	1	-2/+0
2021-06-24	target/mips: Optimize regnames[] arrays	Philippe Mathieu-Daudé	1	-1/+1
2021-05-02	target/mips: Move TCG source files under tcg/ sub directory	Philippe Mathieu-Daudé	1	-11/+0
2021-05-02	target/mips: Move CP0 helpers to sysemu/cp0.c	Philippe Mathieu-Daudé	1	-4/+5
2021-05-02	target/mips: Move exception management code to exception.c	Philippe Mathieu-Daudé	1	-13/+0
2021-05-02	target/mips: Move TLB management helpers to tcg/sysemu/tlb_helper.c	Philippe Mathieu-Daudé	1	-7/+0
2021-05-02	target/mips: Restrict CPUMIPSTLBContext::map_address() handlers scope	Philippe Mathieu-Daudé	1	-6/+0
2021-05-02	target/mips: Move tlb_helper.c to tcg/sysemu/	Philippe Mathieu-Daudé	1	-5/+0
2021-05-02	target/mips: Restrict mmu_init() to TCG	Philippe Mathieu-Daudé	1	-3/+0
2021-05-02	target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCG	Philippe Mathieu-Daudé	1	-4/+0
2021-05-02	target/mips: Move physical addressing code to sysemu/physaddr.c	Philippe Mathieu-Daudé	1	-1/+24
2021-05-02	target/mips: Move cpu_signal_handler definition around	Philippe Mathieu-Daudé	1	-5/+4
2021-05-02	target/mips: Introduce tcg-internal.h for TCG specific declarations	Philippe Mathieu-Daudé	1	-4/+3
2021-05-02	target/mips: Merge do_translate_address into cpu_mips_translate_address	Philippe Mathieu-Daudé	1	-1/+1
2021-05-02	target/mips: Declare mips_env_set_pc() inlined in "internal.h"	Philippe Mathieu-Daudé	1	-0/+10
2021-05-02	target/mips: Restrict mips_cpu_dump_state() to cpu.c	Philippe Mathieu-Daudé	1	-1/+0
2021-05-02	target/mips: Optimize CPU/FPU regnames[] arrays	Philippe Mathieu-Daudé	1	-2/+2
2021-05-02	target/mips: Make CPU/FPU regnames[] arrays global	Philippe Mathieu-Daudé	1	-0/+3
2021-02-21	target/mips: Let CPUMIPSTLBContext::map_address() take MMUAccessType	Philippe Mathieu-Daudé	1	-4/+4
2021-02-21	target/mips: Let cpu_mips_translate_address() take MMUAccessType arg	Philippe Mathieu-Daudé	1	-1/+1
2021-02-21	target/mips: Remove access_type argument from map_address() handler	Philippe Mathieu-Daudé	1	-4/+4
2021-01-14	target/mips: Move msa_reset() to msa_helper.c	Philippe Mathieu-Daudé	1	-0/+2
2021-01-14	target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA	Philippe Mathieu-Daudé	1	-1/+1
2021-01-14	target/mips: Move mmu_init() functions to tlb_helper.c	Philippe Mathieu-Daudé	1	-0/+1
2021-01-14	target/mips: Move common helpers from helper.c to cpu.c	Philippe Mathieu-Daudé	1	-0/+2
2021-01-14	target/mips: Extract FPU helpers to 'fpu_helper.h'	Philippe Mathieu-Daudé	1	-49/+0
2021-01-14	target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6	Philippe Mathieu-Daudé	1	-2/+2
2021-01-14	target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2	Philippe Mathieu-Daudé	1	-1/+1
2021-01-14	target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1	Philippe Mathieu-Daudé	1	-1/+1
2021-01-14	target/mips/mips-defs: Use ISA_MIPS32R6 definition to check Release 6	Philippe Mathieu-Daudé	1	-1/+1
2020-12-13	target/mips: Use FloatRoundMode enum for FCR31 modes conversion	Philippe Mathieu-Daudé	1	-1/+2
2020-12-13	target/mips: Move cpu definitions, reset() and realize() to cpu.c	Philippe Mathieu-Daudé	1	-4/+0
2020-12-13	target/mips: Explicit Release 6 MMU types	Philippe Mathieu-Daudé	1	-4/+5
2020-12-13	target/mips: Include "exec/memattrs.h" in 'internal.h'	Philippe Mathieu-Daudé	1	-0/+1
2020-10-17	target/mips: Move cpu_mips_get_random() with CP0 helpers	Philippe Mathieu-Daudé	1	-1/+1
2020-10-17	target/mips: Fix some comment spelling errors	zhaolichang	1	-1/+1
2020-06-09	target/mips: Add Loongson-3 CPU definition	Huacai Chen	1	-0/+2
2020-06-09	target/mips: fpu: Refactor conversion from ieee to mips exception flags	Aleksandar Markovic	1	-1/+0
2020-03-17	gdbstub: extend GByteArray to read register helpers	Alex Bennée	1	-1/+1
2020-01-29	target/mips: Add implementation of GINVT instruction	Yongbok Kim	1	-0/+1
2019-10-01	target/mips: Clean up internal.h	Aleksandar Markovic	1	-23/+37
2019-09-12	target/mips: Switch to do_transaction_failed() hook	Peter Maydell	1	-3/+5
2019-08-19	target/mips: rationalise softfloat includes	Alex Bennée	1	-0/+7
2019-08-16	migration: Move the VMStateDescription typedef to typedefs.h	Markus Armbruster	1	-1/+1
2019-05-10	target/mips: Convert to CPUClass::tlb_fill	Richard Henderson	1	-2/+3
2019-04-18	qom/cpu: Simplify how CPUClass:cpu_dump_state() prints	Markus Armbruster	1	-2/+1