riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-08-16	target/mips: Add CP0 BadInstrX register	Stefan Markovic	1	-0/+1
2018-08-16	target/mips: Update some CP0 registers bit definitions	Aleksandar Markovic	1	-69/+88
2018-03-19	cpu: get rid of unused cpu_init() defines	Igor Mammedov	1	-2/+0
2018-03-19	cpu: add CPU_RESOLVING_TYPE macro	Igor Mammedov	1	-0/+1
2017-10-27	mips: malta/boston: replace cpu_model with cpu_type	Igor Mammedov	1	-2/+6
2017-09-21	mips: replace cpu_mips_init() with cpu_generic_init()	Igor Mammedov	1	-2/+1
2017-09-21	mips: introduce internal.h and cleanup cpu.h	Philippe Mathieu-Daudé	1	-353/+1
2017-07-20	target/mips: Add segmentation control registers	James Hogan	1	-0/+30
2017-07-20	target/mips: Add an MMU mode for ERL	James Hogan	1	-4/+13
2017-07-20	target/mips: Abstract mmu_idx from hflags	James Hogan	1	-1/+7
2017-07-20	target/mips: Add CP0_Ebase.WG (write gate) support	James Hogan	1	-1/+4
2017-02-21	target-mips: Provide function to test if a CPU supports an ISA	Paul Burton	1	-0/+1
2017-01-13	cputlb: drop flush_global flag from tlb_flush	Alex Bennée	1	-1/+1
2017-01-13	qom/cpu: move tlb_flush to cpu_common_reset	Alex Bennée	1	-0/+3
2016-12-20	Move target-* CPU file into a target/ folder	Thomas Huth	1	-0/+1069