riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-06-09	target/mips: Add Loongson-3 CPU definition	Huacai Chen	1	-2/+30
2020-01-29	target/mips: Add implementation of GINVT instruction	Yongbok Kim	1	-1/+1
2020-01-29	target/mips: Amend CP0 WatchHi register implementation	Yongbok Kim	1	-1/+1
2020-01-15	target/mips: Use cpu__mmuidx_ra instead of MMU_MODE_SUFFIX	Richard Henderson	1	-4/+0
2019-08-29	target/mips: Clean up handling of CP0 register 31	Aleksandar Markovic	1	-1/+1
2019-08-29	target/mips: Clean up handling of CP0 register 29	Aleksandar Markovic	1	-8/+14
2019-08-29	target/mips: Clean up handling of CP0 register 28	Aleksandar Markovic	1	-10/+14
2019-08-29	target/mips: Clean up handling of CP0 register 26	Aleksandar Markovic	1	-1/+1
2019-08-29	target/mips: Clean up handling of CP0 register 23	Aleksandar Markovic	1	-0/+6
2019-08-29	target/mips: Clean up handling of CP0 register 19	Aleksandar Markovic	1	-0/+4
2019-08-29	target/mips: Clean up handling of CP0 register 18	Aleksandar Markovic	1	-8/+12
2019-08-29	target/mips: Clean up handling of CP0 register 16	Aleksandar Markovic	1	-1/+2
2019-08-29	target/mips: Clean up handling of CP0 register 15	Aleksandar Markovic	1	-0/+1
2019-08-29	target/mips: Clean up handling of CP0 register 14	Aleksandar Markovic	1	-0/+1
2019-08-29	target/mips: Clean up handling of CP0 register 13	Aleksandar Markovic	1	-0/+2
2019-08-29	target/mips: Clean up handling of CP0 register 12	Aleksandar Markovic	1	-0/+3
2019-08-29	target/mips: Clean up handling of CP0 register 10	Aleksandar Markovic	1	-0/+1
2019-08-29	target/mips: Clean up handling of CP0 register 8	Aleksandar Markovic	1	-0/+1
2019-08-29	target/mips: Clean up handling of CP0 register 6	Aleksandar Markovic	1	-0/+6
2019-08-29	target/mips: Clean up handling of CP0 register 5	Aleksandar Markovic	1	-0/+6
2019-08-29	target/mips: Clean up handling of CP0 register 4	Aleksandar Markovic	1	-0/+2
2019-08-29	target/mips: Clean up handling of CP0 register 3	Aleksandar Markovic	1	-0/+1
2019-08-29	target/mips: Clean up handling of CP0 register 2	Aleksandar Markovic	1	-0/+7
2019-08-29	target/mips: Clean up handling of CP0 register 1	Aleksandar Markovic	1	-0/+8
2019-08-29	target/mips: Clean up handling of CP0 register 0	Aleksandar Markovic	1	-0/+3
2019-08-20	configure: Define target access alignment in configure	tony.nguyen@bt.com	1	-2/+0
2019-08-19	target/mips: rationalise softfloat includes	Alex Bennée	1	-7/+1
2019-06-12	Include qemu-common.h exactly where needed	Markus Armbruster	1	-1/+0
2019-06-10	cpu: Remove CPU_COMMON	Richard Henderson	1	-2/+0
2019-06-10	cpu: Introduce CPUNegativeOffsetState	Richard Henderson	1	-0/+1
2019-06-10	cpu: Move ENV_OFFSET to exec/gen-icount.h	Richard Henderson	1	-1/+0
2019-06-10	target/mips: Use env_cpu, env_archcpu	Richard Henderson	1	-5/+0
2019-06-10	cpu: Replace ENV_GET_CPU with env_cpu	Richard Henderson	1	-2/+0
2019-06-10	cpu: Define ArchCPU	Richard Henderson	1	-0/+1
2019-06-10	cpu: Define CPUArchState with typedef	Richard Henderson	1	-4/+2
2019-06-10	tcg: Split out target/arch/cpu-param.h	Richard Henderson	1	-2/+1
2019-05-26	target/mips: realign comments to fix checkpatch warnings	Jules Irenge	1	-12/+22
2019-05-26	target/mips: add or remove space to fix checkpatch errors	Jules Irenge	1	-81/+94
2019-04-18	target: Simplify how the TARGET_cpu_list() print	Markus Armbruster	1	-1/+1
2019-02-14	target/mips: introduce MTTCG-enabled builds	Aleksandar Markovic	1	-0/+2
2019-02-14	target/mips: reimplement SC instruction emulation and use cmpxchg	Leon Alrae	1	-4/+0
2019-02-14	target/mips: compare virtual addresses in LL/SC sequence	Leon Alrae	1	-1/+2
2019-01-24	target/mips: Correct the second argument type of cpu_supports_isa()	Aleksandar Markovic	1	-1/+1
2019-01-18	target/mips: Introduce 32 R5900 multimedia registers	Fredrik Noring	1	-0/+3
2019-01-18	target/mips: Add CP0 register MemoryMapID	Aleksandar Markovic	1	-0/+1
2019-01-18	target/mips: Amend preprocessor constants for CP0 registers	Aleksandar Markovic	1	-32/+146
2019-01-18	target/mips: Update ITU to utilize SAARI and SAAR CP0 registers	Yongbok Kim	1	-0/+5
2019-01-18	target/mips: Provide R/W access to SAARI and SAAR CP0 registers	Yongbok Kim	1	-0/+1
2019-01-18	target/mips: Add fields for SAARI and SAAR CP0 registers	Yongbok Kim	1	-2/+8
2019-01-18	target/mips: Add preprocessor constants for 32 major CP0 registers	Aleksandar Markovic	1	-0/+32