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2021-05-02target/mips: Move sysemu specific files under sysemu/ subfolderPhilippe Mathieu-Daudé1-145/+0
Move sysemu-specific files under the new sysemu/ subfolder and adapt the Meson machinery. Update the KVM MIPS entry in MAINTAINERS. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-17-f4bug@amsat.org>
2021-01-14target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2Philippe Mathieu-Daudé1-2/+2
The MIPS ISA release 2 is common to 32/64-bit CPUs. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210104221154.3127610-13-f4bug@amsat.org>
2020-10-17target/mips: Move cp0_count_ns to CPUMIPSStatePhilippe Mathieu-Daudé1-17/+6
Currently the CP0 timer period is fixed at 10 ns, corresponding to a fixed CPU frequency of 200 MHz (using half the speed of the CPU). In few commits we will be able to use a different CPU frequency. In preparation, move the cp0_count_ns variable to CPUMIPSState so we can modify it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Message-Id: <20201012095804.3335117-9-f4bug@amsat.org>
2020-10-17target/mips/cp0_timer: Document TIMER_PERIOD originPhilippe Mathieu-Daudé1-1/+11
TIMER_PERIOD value of '10 ns' can be explained looking at commit 6af0bf9c7c3doc, where the CPU frequency is 200 MHz and CP0 default count rate is half the frequency of the CPU. Document that. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012095804.3335117-8-f4bug@amsat.org>
2020-10-17target/mips/cp0_timer: Explicit unit in variable namePhilippe Mathieu-Daudé1-9/+10
Name variables holding nanoseconds with the '_ns' suffix. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <20201012095804.3335117-7-f4bug@amsat.org>
2020-10-17target/mips: Move cpu_mips_get_random() with CP0 helpersPhilippe Mathieu-Daudé1-25/+0
The get_random() helper uses the CP0_Wired register, which is unrelated to the CP0_Count register used as timer. Commit e16fe40c872 ("Move the MIPS CPU timer in a separate file") incorrectly moved this get_random() helper with timer specific code. Move it back to generic CP0 helpers. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-Id: <20201012095804.3335117-6-f4bug@amsat.org>
2019-08-19target/mips: Style improvements in cp0_timer.cAleksandar Markovic1-19/+23
Fixes mostly errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <1566216496-17375-7-git-send-email-aleksandar.markovic@rt-rk.com>
2019-08-16Include hw/irq.h a lot lessMarkus Armbruster1-0/+1
In my "build everything" tree, changing hw/irq.h triggers a recompile of some 5400 out of 6600 objects (not counting tests and objects that don't depend on qemu/osdep.h). hw/hw.h supposedly includes it for convenience. Several other headers include it just to get qemu_irq and.or qemu_irq_handler. Move the qemu_irq and qemu_irq_handler typedefs from hw/irq.h to qemu/typedefs.h, and then include hw/irq.h only where it's still needed. Touching it now recompiles only some 500 objects. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190812052359.30071-13-armbru@redhat.com>
2017-09-21mips: introduce internal.h and cleanup cpu.hPhilippe Mathieu-Daudé1-0/+1
no logical change, only code movement (and fix a comment typo). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Igor Mammedov <imammedo@redhat.com> Tested-by: James Hogan <james.hogan@imgtec.com> Acked-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-09-21mips: move hw/mips/cputimer.c to target/mips/Philippe Mathieu-Daudé1-0/+164
This timer is a required part of the MIPS32/MIPS64 System Control coprocessor (CP0). Moving it with the other architecture related files will allow an opaque use of CPUMIPSState* in the next commit (introduce "internal.h"). also remove it from 'user' targets, remove an unnecessary include. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Igor Mammedov <imammedo@redhat.com> Tested-by: James Hogan <james.hogan@imgtec.com> Acked-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
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