| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2019-05-10 | tcg: Use CPUClass::tlb_fill in cputlb.c | Richard Henderson | 1 | -6/+0 |
| 2019-05-10 | target/microblaze: Convert to CPUClass::tlb_fill | Richard Henderson | 1 | -50/+57 |
| 2019-04-18 | qom/cpu: Simplify how CPUClass:cpu_dump_state() prints | Markus Armbruster | 1 | -1/+1 |
| 2018-05-29 | target-microblaze: Consolidate MMU enabled checks | Edgar E. Iglesias | 1 | -3/+3 |
| 2018-05-29 | target-microblaze: Make special registers 64-bit | Edgar E. Iglesias | 1 | -5/+10 |
| 2018-05-29 | target-microblaze: Bypass MMU with MMU_NOMMU_IDX | Edgar E. Iglesias | 1 | -1/+2 |
| 2018-05-29 | target-microblaze: Remove USE_MMU PVR checks | Edgar E. Iglesias | 1 | -11/+1 |
| 2018-05-29 | target-microblaze: Tighten up TCGv_i32 vs TCGv type usage | Edgar E. Iglesias | 1 | -1/+1 |
| 2018-01-25 | accel/tcg: add size paremeter in tlb_fill() | Laurent Vivier | 1 | -2/+2 |
| 2016-12-20 | Move target-* CPU file into a target/ folder | Thomas Huth | 1 | -0/+307 |
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index : riscv-gnu-toolchain/qemu.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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