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path: root/target/microblaze/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2020-09-01target/microblaze: Split out EAR from env->sregsRichard Henderson1-0/+1
2020-09-01target/microblaze: Split out MSR from env->sregsRichard Henderson1-3/+4
2020-09-01target/microblaze: Split out PC from env->sregsRichard Henderson1-1/+2
2020-04-30target/microblaze: Add the pvr-user2 propertyEdgar E. Iglesias1-0/+1
2020-04-30target/microblaze: Add the pvr-user1 propertyEdgar E. Iglesias1-0/+1
2020-04-30target/microblaze: Add the unaligned-exceptions propertyEdgar E. Iglesias1-0/+1
2020-04-30target/microblaze: Add the div-zero-exception propertyEdgar E. Iglesias1-0/+1
2020-04-30target/microblaze: Add the ill-opcode-exception propertyEdgar E. Iglesias1-0/+1
2020-04-30target/microblaze: Add the opcode-0x0-illegal CPU propertyEdgar E. Iglesias1-0/+1
2020-03-17gdbstub: extend GByteArray to read register helpersAlex Bennée1-1/+1
2020-01-15target/microblaze: Remove MMU_MODE{0,1,2}_SUFFIXRichard Henderson1-3/+0
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster1-1/+0
2019-06-10cpu: Remove CPU_COMMONRichard Henderson1-2/+0
2019-06-10cpu: Introduce CPUNegativeOffsetStateRichard Henderson1-2/+3
2019-06-10cpu: Move ENV_OFFSET to exec/gen-icount.hRichard Henderson1-1/+0
2019-06-10target/microblaze: Use env_cpu, env_archcpuRichard Henderson1-20/+15
2019-06-10cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson1-2/+0
2019-06-10cpu: Define ArchCPURichard Henderson1-0/+1
2019-06-10cpu: Define CPUArchState with typedefRichard Henderson1-3/+2
2019-06-10tcg: Split out target/arch/cpu-param.hRichard Henderson1-12/+2
2019-05-10target/microblaze: Convert to CPUClass::tlb_fillRichard Henderson1-2/+3
2019-04-18qom/cpu: Simplify how CPUClass:cpu_dump_state() printsMarkus Armbruster1-2/+1
2019-01-22target/microblaze: Add props enabling exceptions on failed bus accessesEdgar E. Iglesias1-0/+2
2019-01-22target/microblaze: Switch to transaction_failed hookPeter Maydell1-3/+4
2018-05-29target-microblaze: Consolidate MMU enabled checksEdgar E. Iglesias1-1/+3
2018-05-29target-microblaze: cpu_mmu_index: Fixup indentationEdgar E. Iglesias1-7/+9
2018-05-29target-microblaze: Convert env_btarget to i64Edgar E. Iglesias1-1/+1
2018-05-29target-microblaze: Add Extended AddressingEdgar E. Iglesias1-0/+2
2018-05-29target-microblaze: Setup for 64bit addressingEdgar E. Iglesias1-3/+3
2018-05-29target-microblaze: Make special registers 64-bitEdgar E. Iglesias1-1/+1
2018-05-29target-microblaze: Use TCGv for load/store addressesEdgar E. Iglesias1-1/+1
2018-05-29target-microblaze: Correct the PVR array sizeEdgar E. Iglesias1-1/+1
2018-05-29target-microblaze: Correct special register array sizesEdgar E. Iglesias1-2/+2
2018-03-19cpu: get rid of unused cpu_init() definesIgor Mammedov1-1/+0
2018-03-19cpu: add CPU_RESOLVING_TYPE macroIgor Mammedov1-0/+1
2018-02-21target/*/cpu.h: remove softfloat.hAlex Bennée1-1/+1
2018-01-25accel/tcg: add size paremeter in tlb_fill()Laurent Vivier1-1/+1
2017-09-01microblaze: replace cpu_mb_init() with cpu_generic_init()Igor Mammedov1-2/+1
2017-07-04target-microblaze: Introduce a use-pcmp-instr propertyEdgar E. Iglesias1-0/+1
2017-07-04target-microblaze: Introduce a use-msr-instr propertyEdgar E. Iglesias1-0/+1
2017-07-04target-microblaze: Introduce a use-hw-mul propertyEdgar E. Iglesias1-0/+1
2017-07-04target-microblaze: Introduce a use-div propertyEdgar E. Iglesias1-0/+1
2017-07-04target-microblaze: Introduce a use-barrel propertyEdgar E. Iglesias1-0/+1
2017-07-04target-microblaze: Correct bit shift for the PVR0 version fieldEdgar E. Iglesias1-0/+2
2017-01-13qom/cpu: move tlb_flush to cpu_common_resetAlex Bennée1-0/+3
2016-12-20Move target-* CPU file into a target/ folderThomas Huth1-0/+381
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