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2018-01-04target/m68k: add move16Laurent Vivier3-1/+82
move16 moves the source line to the destination line. Lines are aligned to 16-byte boundaries and are 16 bytes long. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-9-laurent@vivier.eu>
2018-01-04target/m68k: add chk and chk2Laurent Vivier5-1/+143
chk and chk2 compare a value to boundaries, and trigger a CHK exception if the value is out of bounds. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-8-laurent@vivier.eu>
2018-01-04target/m68k: manage 680x0 stack framesLaurent Vivier3-7/+164
680x0 manages several stack frame formats: - format 0: four-word stack frame - format 1: four-word throwaway stack frame - format 2: six-word stack frame - format 3: Floating-Point post-instruction stack frame - format 4: eight-word stack frame - format 7: access-error stack frame Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-7-laurent@vivier.eu>
2018-01-04target/m68k: add CPU_LOG_INT traceLaurent Vivier2-2/+123
Display the interrupts/exceptions information in QEMU logs (-d int) Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-6-laurent@vivier.eu>
2018-01-04target/m68k: use insn_pc to generate instruction fault addressLaurent Vivier1-20/+20
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-5-laurent@vivier.eu>
2018-01-04target/m68k: fix gen_get_ccr()Laurent Vivier1-1/+0
As gen_helper_get_ccr() is able to compute CCR from cc_op and flags, we don't need to flush flags before to call it. flush_flags() and get_ccr() use COMPUTE_CCR() to compute flags. get_ccr() computes CCR value, whereas flush_flags update live cc_op and flags. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-3-laurent@vivier.eu>
2018-01-04target-m68k: sync CC_OP before gen_jmp_tb()Laurent Vivier1-1/+2
And remove update_cc_op() from gen_exception() because there is one in gen_jmp_im(). Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-2-laurent@vivier.eu>
2017-12-29tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED*Richard Henderson1-7/+7
These are now trivial sets and tests against NULL. Unwrap. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-12-27target/*helper: don't check retaddr before calling cpu_restore_stateAlex Bennée1-5/+2
cpu_restore_state officially supports being passed an address it can't resolve the state for. As a result the checks in the helpers are superfluous and can be removed. This makes the code consistent with other users of cpu_restore_state. Of course this does nothing to address what to do if cpu_restore_state can't resolve the state but so far it seems this is handled elsewhere. The change was made with included coccinelle script. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> [rth: Fixed up comment indentation. Added second hunk to script to combine cpu_restore_state and cpu_loop_exit.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-12-21target/m68k: fix set_cc_op()Laurent Vivier2-1/+2
The first call of set_cc_op() in a new translation sequence is done with old_op set to CC_OP_DYNAMIC (-1). This will do an out of bound access to the array cc_op_live[]. We fix that by adding an entry in cc_op_live[] for CC_OP_DYNAMIC. Reported-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20171221160558.14151-1-laurent@vivier.eu>
2017-12-21target/m68k: add monitor.cLaurent Vivier2-0/+40
This allows to use registers content in the monitor. Example: BEFORE: (qemu) print $d0 unknown register AFTER: (qemu) print $d0 0 (qemu) print $sr 0x2000 (qemu) x/10i $pc 0x40010a2a: movew %sr,%d0 0x40010a2c: oril #1792,%d0 0x40010a32: movew %d0,%sr 0x40010a34: movel %a0@,%d0 0x40010a36: btst #3,%d0 0x40010a3a: beqs 0x40010a26 0x40010a3c: movew %sr,%d0 0x40010a3e: andil #63743,%d0 0x40010a44: movew %d0,%sr 0x40010a46: rts Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Message-Id: <20171221083057.17942-1-laurent@vivier.eu>
2017-12-21target/m68k: remove unused variable gen_throws_exceptionLaurent Vivier1-10/+0
It has been introduced by e6e5906b6e ("ColdFire target."), but the content is never used. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Message-Id: <20171220130815.20708-1-laurent@vivier.eu>
2017-10-30Merge remote-tracking branch ↵Peter Maydell2-48/+30
'remotes/ehabkost/tags/x86-and-machine-pull-request' into staging x86/cpu/numa queue, 2017-10-27 # gpg: Signature made Fri 27 Oct 2017 15:17:12 BST # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-and-machine-pull-request: (39 commits) x86: Skip check apic_id_limit for Xen numa: fixup parsed NumaNodeOptions earlier mips: r4k: replace cpu_model with cpu_type mips: mipssim: replace cpu_model with cpu_type mips: Magnum/Acer Pica 61: replace cpu_model with cpu_type mips: fulong2e: replace cpu_model with cpu_type mips: malta/boston: replace cpu_model with cpu_type mips: use object_new() instead of gnew()+object_initialize() sparc: leon3: use generic cpu_model parsing sparc: sparc: use generic cpu_model parsing sparc: sun4u/sun4v/niagara: use generic cpu_model parsing sparc: cleanup cpu type name composition tricore: use generic cpu_model parsing tricore: cleanup cpu type name composition unicore32: use generic cpu_model parsing unicore32: cleanup cpu type name composition xtensa: lx60/lx200/ml605/kc705: use generic cpu_model parsing xtensa: sim: use generic cpu_model parsing xtensa: cleanup cpu type name composition sh4: remove SuperHCPUClass::name field ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-27m68k: cleanup cpu type name compositionIgor Mammedov2-48/+30
use new M68K_CPU_TYPE_NAME to compose CPU type names and get rid of intermediate M68kCPUInfo/register_cpu_type() which is replaced by static TypeInfo array. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <1507211474-188400-12-git-send-email-imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-10-27Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell1-1/+1
Capstone disassembler # gpg: Signature made Thu 26 Oct 2017 10:57:27 BST # gpg: using RSA key 0x64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-dis-20171026: disas: Add capstone as submodule disas: Remove monitor_disas_is_physical ppc: Support Capstone in disas_set_info arm: Support Capstone in disas_set_info i386: Support Capstone in disas_set_info disas: Support the Capstone disassembler library disas: Remove unused flags arguments target/arm: Don't set INSN_ARM_BE32 for CONFIG_USER_ONLY target/arm: Move BE32 disassembler fixup target/ppc: Convert to disas_set_info hook target/i386: Convert to disas_set_info hook Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # target/i386/cpu.c # target/ppc/translate_init.c
2017-10-25disas: Remove unused flags argumentsRichard Henderson1-1/+1
Now that every target is using the disas_set_info hook, the flags argument is unused. Remove it. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-24tcg: Initialize cpu_env genericallyRichard Henderson1-5/+0
This is identical for each target. So, move the initialization to common code. Move the variable itself out of tcg_ctx and name it cpu_env to minimize changes within targets. This also means we can remove tcg_global_reg_new_{ptr,i32,i64}, since there are no longer global-register temps created by targets. Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-24tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota1-1/+1
Groundwork for supporting multiple TCG contexts. The core of this patch is this change to tcg/tcg.h: > -extern TCGContext tcg_ctx; > +extern TCGContext tcg_init_ctx; > +extern TCGContext *tcg_ctx; Note that for now we set *tcg_ctx to whatever TCGContext is passed to tcg_context_init -- in this case &tcg_init_ctx. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-24target/m68k: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota3-15/+31
Thereby decoupling the resulting translated code from the current state of the system. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-24tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota1-3/+3
Convert all existing readers of tb->cflags to tb_cflags, so that we use atomic_read and therefore avoid undefined behaviour in C11. Note that the remaining setters/getters of the field are protected by tb_lock, and therefore do not need conversion. Luckily all readers access the field via 'tb->cflags' (so no foo.cflags, bar->cflags in the code base), which makes the conversion easily scriptable: FILES=$(git grep 'tb->cflags' target include/exec/gen-icount.h \ accel/tcg/translator.c | cut -f1 -d':' | sort | uniq) perl -pi -e 's/([^.>])tb->cflags/$1tb_cflags(tb)/g' $FILES perl -pi -e 's/([a-z->.]*)(->|\.)tb->cflags/tb_cflags($1$2tb)/g' $FILES Then manually fixed the few errors that checkpatch reported. Compile-tested for all targets. Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-24qom: Introduce CPUClass.tcg_initializeRichard Henderson1-6/+1
Move target cpu tcg initialization to common code, called from cpu_exec_realizefn. Acked-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-24tcg: Remove TCGV_EQUAL*Richard Henderson1-1/+1
When we used structures for TCGv_*, we needed a macro in order to perform a comparison. Now that we use pointers, this is just clutter. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-09qom/cpu: move cpu_model null check to cpu_class_by_name()Philippe Mathieu-Daudé1-4/+0
and clean every implementation. Suggested-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20170917232842.14544-1-f4bug@amsat.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-09-10target/m68k: Switch fpu_rom from make_floatx80() to make_floatx80_init()Kamil Rytarowski1-22/+22
GCC 4.7.2 on SunOS reports that the values assigned to array members are not real constants: target/m68k/fpu_helper.c:32:5: error: initializer element is not constant target/m68k/fpu_helper.c:32:5: error: (near initialization for 'fpu_rom[0]') rules.mak:66: recipe for target 'target/m68k/fpu_helper.o' failed Convert the array to make_floatx80_init() to fix it. Replace floatx80_pi-like constants with make_floatx80_init() as they are defined as make_floatx80(). This fixes build on SmartOS (Joyent). Signed-off-by: Kamil Rytarowski <n54@gmx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20170904212306.3020-1-n54@gmx.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-09-06target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova1-1/+6
Used later. An enum makes expected values explicit and bounds the value space of switches. Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <150002049746.22386.2316077281615710615.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-09-01m68k: replace cpu_m68k_init() with cpu_generic_init()Igor Mammedov3-22/+3
call register_m68k_insns() at realize time which makes cpu_m68k_init() typical object creation function. As result we can replace it with cpu_generic_init() which does the same job, reducing code duplication a bit. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Tested-by: Thomas Huth <huth@tuxfamily.org> Acked-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <1503592308-93913-12-git-send-email-imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-07-31m68k/translate: fix incorrect copy/pastePhilippe Mathieu-Daudé1-1/+1
db3d7945ae extended gen_cc_cond() for cond [6, 7, 9, 10] but misswrote [4, 5] target/m68k/translate.c:1323:70: warning: identical expressions on both sides of logical operator if (op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL || op == CC_OP_ADDB || op == CC_OP_ADDW || op == CC_OP_ADDL) { ~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~ ^ Reported-by: Clang Static Analyzer Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova1-3/+2
Needed to implement a target-agnostic gen_intermediate_code() in the future. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Benneé <alex.benee@linaro.org> Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-Id: <150002025498.22386.18051908483085660588.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-19target/m68k: optimize bcd_flags() using extract opPhilippe Mathieu-Daudé1-2/+1
Done with the Coccinelle semantic patch scripts/coccinelle/tcg_gen_extract.cocci. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718045540.16322-5-f4bug@amsat.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-29target/m68k: add fmovemLaurent Vivier3-30/+189
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170628204241.32106-8-laurent@vivier.eu>
2017-06-29target/m68k: add explicit single and double precision operations (part 2)Laurent Vivier3-8/+74
Add fsabs, fdabs, fsneg, fdneg, fsmove and fdmove. The value is converted using the new floatx80_round() function. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170628204241.32106-7-laurent@vivier.eu>
2017-06-29target/m68k: add fsglmul and fsgldivLaurent Vivier3-0/+36
fsglmul and fsgldiv truncate data to single precision before computing results. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170628204241.32106-6-laurent@vivier.eu>
2017-06-29target/m68k: add explicit single and double precision operationsLaurent Vivier3-5/+125
Add fssqrt, fdsqrt, fsadd, fdadd, fssub, fdsub, fsmul, fdmul, fsdiv, fddiv. The precision is managed using set_floatx80_rounding_precision(). Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170628204241.32106-4-laurent@vivier.eu>
2017-06-29target/m68k: add fmovecrLaurent Vivier3-1/+47
fmovecr moves a floating point constant from the FPU ROM to a floating point register. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20170628204241.32106-3-laurent@vivier.eu>
2017-06-29target/m68k: add fscc.Laurent Vivier1-79/+131
use DisasCompare with FPU conditions in fscc and fbcc. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170628204241.32106-2-laurent@vivier.eu>
2017-06-21target-m68k: add FPCR and FPSRLaurent Vivier6-119/+421
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170620205121.26515-6-laurent@vivier.eu>
2017-06-21target-m68k: define 96bit FP registers for gdb on 680x0Laurent Vivier1-0/+45
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170620205121.26515-5-laurent@vivier.eu>
2017-06-21target-m68k: use floatx80 internallyLaurent Vivier7-291/+509
Coldfire uses float64, but 680x0 use floatx80. This patch introduces the use of floatx80 internally and enables 680x0 80bits FPU. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170620205121.26515-4-laurent@vivier.eu>
2017-06-21target-m68k: initialize FPU registersLaurent Vivier1-1/+8
on reset, set FP registers to NaN and control registers to 0 Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170620205121.26515-3-laurent@vivier.eu>
2017-06-21target-m68k: move fmove CR to a functionLaurent Vivier1-25/+31
Move code of fmove to/from control register to a function Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20170620205121.26515-2-laurent@vivier.eu>
2017-06-15target-m68k: define ext_opsizeLaurent Vivier1-19/+24
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170611231633.32582-4-laurent@vivier.eu>
2017-06-15target-m68k: move FPU helpers to fpu_helper.cLaurent Vivier3-89/+113
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170611231633.32582-3-laurent@vivier.eu>
2017-06-15target/m68k: fix V flag for CC_OP_SUBxLaurent Vivier1-1/+1
V flag for subtraction is: v = (res ^ src1) & (src1 ^ src2) (see COMPUTE_CCR() in target/m68k/helper.c) But gen_flush_flags() uses: v = (res ^ src2) & (src1 ^ src2) The problem has been found with the following program: .global _start _start: move.l #-2147483648,%d0 subq.l #1,%d0 jvc 1f move.l #1,%d1 move.l #1,%d0 trap #0 1: move.l #0,%d1 move.l #1,%d0 trap #0 It works fine (exit(1)) on real hardware, and with "-singlestep". "-singlestep" uses gen_helper_flush_flags(), whereas without "-singlestep", V flag is computed directly in gen_flush_flags(). This patch updates gen_flush_flags() to have the same result as with gen_helper_flush_flags(). Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170614203905.19657-1-laurent@vivier.eu>
2017-06-07target/m68k: implement rtdLaurent Vivier3-0/+14
Add "Return and Deallocate" (rtd) instruction. RTD #d (SP) -> PC SP + 4 + d -> SP Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Tested-By: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> Message-Id: <20170605100014.22981-1-laurent@vivier.eu>
2017-01-16Merge remote-tracking branch ↵Peter Maydell2-2/+4
'remotes/stsquad/tags/pull-tcg-common-tlb-reset-20170113-r1' into staging This is the same as the v3 posted except a re-base and a few extra signoffs # gpg: Signature made Fri 13 Jan 2017 14:26:46 GMT # gpg: using RSA key 0xFBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-tcg-common-tlb-reset-20170113-r1: cputlb: drop flush_global flag from tlb_flush cpu_common_reset: wrap TCG specific code in tcg_enabled() qom/cpu: move tlb_flush to cpu_common_reset Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-14target-m68k: increment/decrement with SPLaurent Vivier1-2/+12
On 680x0 family only. Address Register indirect With postincrement: When using the stack pointer (A7) with byte size data, the register is incremented by two. Address Register indirect With predecrement: When using the stack pointer (A7) with byte size data, the register is decremented by two. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <1484332593-16782-6-git-send-email-laurent@vivier.eu>
2017-01-14target-m68k: CAS doesn't need aligned accessLaurent Vivier1-1/+0
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <1484332593-16782-5-git-send-email-laurent@vivier.eu>
2017-01-14target-m68k: manage pre-dec et post-inc in CASLaurent Vivier1-0/+9
In these cases we must update the address register after the operation. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <1484332593-16782-4-git-send-email-laurent@vivier.eu>
2017-01-14target-m68k: fix gen_flush_flags()Laurent Vivier1-1/+2
gen_flush_flags() is setting unconditionally cc_op_synced to 1 and s->cc_op to CC_OP_FLAGS, whereas env->cc_op can be set to something else by a previous tcg fragment. We fix that by not setting cc_op_synced to 1 (except for gen_helper_flush_flags() that updates env->cc_op) FIX: https://github.com/vivier/qemu-m68k/issues/19 Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <1484332593-16782-3-git-send-email-laurent@vivier.eu>
2017-01-14target-m68k: fix bit operation with immediate valueLaurent Vivier1-3/+10
M680x0 bit operations with an immediate value use 9 bits of the 16bit value, while coldfire ones use only 8 bits. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <1484332593-16782-2-git-send-email-laurent@vivier.eu>
generated by cgit v1.1 at 2025-01-24 00:01:19 +0000