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2018-03-20Merge remote-tracking branch ↵Peter Maydell1-36/+66
'remotes/vivier/tags/m68k-for-2.12-pull-request' into staging # gpg: Signature made Tue 20 Mar 2018 09:07:55 GMT # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/m68k-for-2.12-pull-request: target/m68k: add a mechanism to automatically free TCGv target/m68k: add DisasContext parameter to gen_extend() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-03-20target/m68k: add a mechanism to automatically free TCGvLaurent Vivier1-13/+43
SRC_EA() and gen_extend() can return either a temporary TCGv or a memory allocated one. Mark them when they are allocated, and free them automatically at end of the instruction translation. We want to free locally allocated TCGv to avoid overflow in sequence like: 0xc00ae406: movel %fp@(-132),%fp@(-268) 0xc00ae40c: movel %fp@(-128),%fp@(-264) 0xc00ae412: movel %fp@(-20),%fp@(-212) 0xc00ae418: movel %fp@(-16),%fp@(-208) 0xc00ae41e: movel %fp@(-60),%fp@(-220) 0xc00ae424: movel %fp@(-56),%fp@(-216) 0xc00ae42a: movel %fp@(-124),%fp@(-252) 0xc00ae430: movel %fp@(-120),%fp@(-248) 0xc00ae436: movel %fp@(-12),%fp@(-260) 0xc00ae43c: movel %fp@(-8),%fp@(-256) 0xc00ae442: movel %fp@(-52),%fp@(-276) 0xc00ae448: movel %fp@(-48),%fp@(-272) ... That can fill a lot of TCGv entries in a sequence, especially since 15fa08f845 ("tcg: Dynamically allocate TCGOps") we have no limit to fill the TCGOps cache and we can fill the entire TCG variables array and overflow it. Suggested-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180319113544.704-3-laurent@vivier.eu>
2018-03-20target/m68k: add DisasContext parameter to gen_extend()Laurent Vivier1-23/+23
This parameter will be needed to manage automatic release of temporary allocated TCG variables. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180319113544.704-2-laurent@vivier.eu>
2018-03-19cpu: get rid of unused cpu_init() definesIgor Mammedov1-2/+0
cpu_init(cpu_model) were replaced by cpu_create(cpu_type) so no users are left, remove it. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> (ppc) Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1518000027-274608-6-git-send-email-imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-03-19cpu: add CPU_RESOLVING_TYPE macroIgor Mammedov1-0/+1
it will be used for providing to cpu name resolving class for parsing cpu model for system and user emulation code. Along with change add target to null-machine tests, so that when switch to CPU_RESOLVING_TYPE happens, it would ensure that null-machine usecase still works. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> (m68k) Acked-by: David Gibson <david@gibson.dropbear.id.au> (ppc) Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (tricore) Message-Id: <1518000027-274608-4-git-send-email-imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> [ehabkost: Added macro to riscv too] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-03-13target/m68k: implement fcoshLaurent Vivier5-0/+91
Using a local m68k floatx80_cosh() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180312202728.23790-12-laurent@vivier.eu>
2018-03-13target/m68k: implement fsinhLaurent Vivier5-0/+99
Using a local m68k floatx80_sinh() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180312202728.23790-11-laurent@vivier.eu>
2018-03-13target/m68k: implement ftanhLaurent Vivier5-0/+377
Using local m68k floatx80_tanh() and floatx80_etoxm1() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180312202728.23790-10-laurent@vivier.eu>
2018-03-13target/m68k: implement fatanhLaurent Vivier5-0/+75
Using a local m68k floatx80_atanh() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180312202728.23790-9-laurent@vivier.eu>
2018-03-13target/m68k: implement facosLaurent Vivier5-0/+80
Using a local m68k floatx80_acos() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180312202728.23790-8-laurent@vivier.eu>
2018-03-13target/m68k: implement fasinLaurent Vivier5-0/+75
Using a local m68k floatx80_asin() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180312202728.23790-7-laurent@vivier.eu>
2018-03-13target/m68k: implement fatanLaurent Vivier6-0/+341
Using a local m68k floatx80_atan() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180312202728.23790-6-laurent@vivier.eu>
2018-03-13target/m68k: implement fsincosLaurent Vivier3-0/+20
using floatx80_sin() and floatx80_cos() Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180312202728.23790-5-laurent@vivier.eu>
2018-03-13target/m68k: implement fcosLaurent Vivier5-0/+254
Using a local m68k floatx80_cos() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180312202728.23790-4-laurent@vivier.eu>
2018-03-13target/m68k: implement fsinLaurent Vivier5-0/+257
Using a local m68k floatx80_sin() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180312202728.23790-3-laurent@vivier.eu>
2018-03-13target/m68k: implement ftanLaurent Vivier6-0/+356
Using a local m68k floatx80_tan() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180312202728.23790-2-laurent@vivier.eu>
2018-03-09target/m68k: implement ftentoxLaurent Vivier5-0/+163
Using a local m68k floatx80_tentox() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180305203910.10391-9-laurent@vivier.eu>
2018-03-09target/m68k: implement ftwotoxLaurent Vivier6-0/+244
Using a local m68k floatx80_twotox() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180305203910.10391-8-laurent@vivier.eu>
2018-03-09target/m68k: implement fetoxLaurent Vivier6-0/+327
Using a local m68k floatx80_etox() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180305203910.10391-7-laurent@vivier.eu>
2018-03-09target/m68k: implement flog2Laurent Vivier5-0/+77
Using a local m68k floatx80_log2() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180305203910.10391-6-laurent@vivier.eu>
2018-03-09target/m68k: implement flog10Laurent Vivier5-0/+67
Using a local m68k floatx80_log10() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180305203910.10391-5-laurent@vivier.eu>
2018-03-09target/m68k: implement flognLaurent Vivier5-0/+178
Using a local m68k floatx80_logn() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180305203910.10391-4-laurent@vivier.eu>
2018-03-09target/m68k: implement flognp1Laurent Vivier6-0/+380
Using a local m68k floatx80_lognp1() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180305203910.10391-3-laurent@vivier.eu>
2018-03-09target/m68k: define floatx80_move()Laurent Vivier2-0/+28
This functions is needed by upcoming m68k softfloat functions. Source code copied for WinUAE (tag 3500) (The WinUAE file has been copied from QEMU and has the QEMU licensing notice) Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180305203910.10391-2-laurent@vivier.eu>
2018-03-04target/m68k: add fscale, fgetman and fgetexpLaurent Vivier5-0/+174
Using local m68k floatx80_getman(), floatx80_getexp(), floatx80_scale() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180224201802.911-5-laurent@vivier.eu>
2018-03-04target/m68k: add fmod/fremLaurent Vivier7-2/+176
Using a local m68k floatx80_mod() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] The quotient byte of the FPSR is updated with the result of the operation. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180224201802.911-3-laurent@vivier.eu>
2018-03-04target/m68k: TCGv returned by gen_load() must be freedLaurent Vivier1-0/+11
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180217235920.2254-1-laurent@vivier.eu>
2018-02-21target/*/cpu.h: remove softfloat.hAlex Bennée5-2/+5
As cpu.h is another typically widely included file which doesn't need full access to the softfloat API we can remove the includes from here as well. Where they do need types it's typically for float_status and the rounding modes so we move that to softfloat-types.h as well. As a result of not having softfloat in every cpu.h call we now need to add it to various helpers that do need the full softfloat.h definitions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [For PPC parts] Acked-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-14m68k: implement movep instructionPavel Dovgalyuk3-0/+49
This patch implements movep instruction. It moves data between a data register and alternate bytes within the address space starting at the location specified and incrementing by two. It was designed for the original 68000 and used in firmwares for interfacing the 8-bit peripherals through the 16-bit data bus. Without this patch opcode for this instruction is recognized as some bitop. Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Signed-off-by: Mihail Abakumov <mikhail.abakumov@ispras.ru> Tested-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180206124431.31433.91946.stgit@pasha-VirtualBox> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-02-05qdev: use device_class_set_parent_realize/unrealize/reset()Philippe Mathieu-Daudé1-3/+2
changes generated using the following Coccinelle patch: @@ type DeviceParentClass; DeviceParentClass *pc; DeviceClass *dc; identifier parent_fn; identifier child_fn; @@ ( +device_class_set_parent_realize(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->realize; ... -dc->realize = child_fn; | +device_class_set_parent_unrealize(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->unrealize; ... -dc->unrealize = child_fn; | +device_class_set_parent_reset(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->reset; ... -dc->reset = child_fn; ) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180114020412.26160-4-f4bug@amsat.org> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-01-25target/m68k: add HMP command "info tlb"Laurent Vivier3-0/+235
Dump MMU state and address mappings. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180118193846.24953-8-laurent@vivier.eu>
2018-01-25target/m68k: add pflush/ptestLaurent Vivier6-0/+113
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180118193846.24953-7-laurent@vivier.eu>
2018-01-25target/m68k: add movesLaurent Vivier5-7/+98
and introduce SFC and DFC control registers. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180118193846.24953-6-laurent@vivier.eu>
2018-01-25target/m68k: add index parameter to gen_load()/gen_store() and Co.Laurent Vivier1-59/+66
The instruction "moves" can select source and destination address space (user or kernel). This patch modifies all the load/store functions to be able to provide the address space the caller wants to use instead of using the current one. All the callers are modified to provide the default address space to these functions. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180118193846.24953-5-laurent@vivier.eu>
2018-01-25target/m68k: add Transparent TranslationLaurent Vivier4-0/+104
Add ittr0, ittr1, dttr0, dttr1 and manage Transparent Translations Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180118193846.24953-4-laurent@vivier.eu>
2018-01-25target/m68k: add MC68040 MMULaurent Vivier6-16/+423
Only add MC68040 MMU page table processing and related registers (Special Status Word, Translation Control Register, User Root Pointer and Supervisor Root Pointer). Transparent Translation Registers, DFC/SFC and pflush/ptest will be added later. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180118193846.24953-3-laurent@vivier.eu>
2018-01-25accel/tcg: add size paremeter in tlb_fill()Laurent Vivier3-6/+6
The MC68040 MMU provides the size of the access that triggers the page fault. This size is set in the Special Status Word which is written in the stack frame of the access fault exception. So we need the size in m68k_cpu_unassigned_access() and m68k_cpu_handle_mmu_fault(). To be able to do that, this patch modifies the prototype of handle_mmu_fault handler, tlb_fill() and probe_write(). do_unassigned_access() already includes a size parameter. This patch also updates handle_mmu_fault handlers and tlb_fill() of all targets (only parameter, no code change). Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180118193846.24953-2-laurent@vivier.eu>
2018-01-25target/m68k: fix TCG variable double freeLaurent Vivier1-1/+0
t64 is also unconditionally freed after the switch () { ... } Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180119114444.7590-1-laurent@vivier.eu>
2018-01-08Merge remote-tracking branch ↵Peter Maydell8-126/+926
'remotes/vivier/tags/m68k-for-2.12-pull-request' into staging # gpg: Signature made Thu 04 Jan 2018 16:37:32 GMT # gpg: using RSA key 0xF30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/m68k-for-2.12-pull-request: target/m68k: fix m68k_cpu_dump_state() target/m68k: add the Interrupt Stack Pointer target/m68k: add andi/ori/eori to SR/CCR target/m68k: add 680x0 "move to SR" instruction target/m68k: move CCR/SR functions target/m68k: implement fsave/frestore target/m68k: add reset target/m68k: add cpush/cinv target/m68k: softmmu cleanup target/m68k: add move16 target/m68k: add chk and chk2 target/m68k: manage 680x0 stack frames target/m68k: add CPU_LOG_INT trace target/m68k: use insn_pc to generate instruction fault address linux-user, m68k: correctly manage SR in context target/m68k: fix gen_get_ccr() target-m68k: sync CC_OP before gen_jmp_tb() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-01-04target/m68k: fix m68k_cpu_dump_state()Laurent Vivier2-4/+8
Display correctly the Trace bits for 680x0 (2 bits instead of 1 for Coldfire). Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-18-laurent@vivier.eu>
2018-01-04target/m68k: add the Interrupt Stack PointerLaurent Vivier7-17/+190
Add the third stack pointer, the Interrupt Stack Pointer (ISP) (680x0 only). This stack will be needed in softmmu mode. Update movec to set/get the value of the three stacks. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-17-laurent@vivier.eu>
2018-01-04target/m68k: add andi/ori/eori to SR/CCRLaurent Vivier1-7/+46
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-16-laurent@vivier.eu>
2018-01-04target/m68k: add 680x0 "move to SR" instructionLaurent Vivier1-16/+22
Some cleanup, and allows SR to be moved from any addressing mode. Previous code was wrong for coldfire: coldfire also allows to use addressing mode to set SR/CCR. It only supports Data register to get SR/CCR (move from) Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-15-laurent@vivier.eu>
2018-01-04target/m68k: move CCR/SR functionsLaurent Vivier1-56/+55
The following patches will be clearer if we move functions before adding new ones. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-14-laurent@vivier.eu>
2018-01-04target/m68k: implement fsave/frestoreLaurent Vivier1-8/+15
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-13-laurent@vivier.eu>
2018-01-04target/m68k: add resetLaurent Vivier3-0/+24
The instruction traps if the CPU is not in Supervisor state but the helper is empty because there is no easy way to reset all the peripherals without resetting the CPU itself. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-12-laurent@vivier.eu>
2018-01-04target/m68k: add cpush/cinvLaurent Vivier1-0/+20
Add cache lines invalidate and cache lines push as no-op operations, as we don't have cache. These instructions are 68040 only. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-11-laurent@vivier.eu>
2018-01-04target/m68k: softmmu cleanupLaurent Vivier1-6/+33
don't compile supervisor only instructions in linux-user mode Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-10-laurent@vivier.eu>
2018-01-04target/m68k: add move16Laurent Vivier3-1/+82
move16 moves the source line to the destination line. Lines are aligned to 16-byte boundaries and are 16 bytes long. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-9-laurent@vivier.eu>
2018-01-04target/m68k: add chk and chk2Laurent Vivier5-1/+143
chk and chk2 compare a value to boundaries, and trigger a CHK exception if the value is out of bounds. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-8-laurent@vivier.eu>
generated by cgit v1.1 at 2025-02-10 13:29:34 +0000