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2023-06-20target/m68k: Check for USER_ONLY definition instead of SOFTMMU onePhilippe Mathieu-Daudé1-1/+1
Since we *might* have user emulation with softmmu, replace the system emulation check by !user emulation one. Invert some if() ladders for clarity. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230613133347.82210-4-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-02target/m68k: Mark helper_raise_exception as noreturnRichard Henderson1-1/+1
Also mark raise_exception_ra and raise_exception, lest we generate a warning about helper_raise_exception returning. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220602013401.303699-18-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-06-02target/m68k: Fix pc, c flag, and address argument for EXCP_DIV0Richard Henderson1-6/+6
According to the M68040 Users Manual, section 8.4.3, Six word stack frame (format 2), Zero Div (and others) is supposed to record the next insn in PC and the address of the trapping instruction in ADDRESS. While the N, Z and V flags are documented to be undefine on DIV0, the C flag is documented as always cleared. Update helper_div* to take the instruction length as an argument and use raise_exception_format2. Hoist the reset of the C flag above the division by zero check. Update m68k_interrupt_all to pass mmu.ar to do_stack_frame. Update cpu_loop to pass mmu.ar to siginfo.si_addr, as the kernel does in trap_c(). Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220602013401.303699-8-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-02-28tcg: Remove dh_alias indirection for dh_typecodeRichard Henderson1-0/+1
The dh_alias redirect is intended to handle TCG types as distinguished from C types. TCG does not distinguish signed int from unsigned int, because they are the same size. However, we need to retain this distinction for dh_typecode, lest we fail to extend abi types properly for the host call parameters. This bug was detected when running the 'arm' emulator on an s390 system. The s390 uses TCG_TARGET_EXTEND_ARGS which triggers code in tcg_gen_callN to extend 32 bit values to 64 bits; the incorrect sign data in the typemask for each argument caused the values to be extended as unsigned values. This simple program exhibits the problem: static volatile int num = -9; static volatile int den = -5; int main(void) { int quo = num / den; printf("num %d den %d quo %d\n", num, den, quo); exit(0); } When run on the broken qemu, this results in: num -9 den -5 quo 0 The correct result is: num -9 den -5 quo 1 Fixes: 7319d83a735 ("tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/876 Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reported-by: Christian Ehrhardt <christian.ehrhardt@canonical.com> Tested-by: Christian Ehrhardt <christian.ehrhardt@canonical.com> Tested-by: Keith Packard <keithp@keithp.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-19tcg: Combine dh_is_64bit and dh_is_signed to dh_typecodeRichard Henderson1-1/+0
We will shortly be interested in distinguishing pointers from integers in the helper's declaration, as well as a true void return. We currently have two parallel 1 bit fields; merge them and expand to a 3 bit field. Our current maximum is 7 helper arguments, plus the return makes 8 * 3 = 24 bits used within the uint32_t typemask. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-06-02target/m68k: implement opcode fetoxm1Laurent Vivier1-0/+1
Example provided in the launchpad bug fails with: qemu: uncaught target signal 4 (Illegal instruction) - core dumped Illegal instruction (core dumped) It appears fetoxm1 is not implemented: IN: expm1f 0x800005cc: fetoxm1x %fp2,%fp0 Disassembler disagrees with translator over instruction decoding Please report this to qemu-devel@nongnu.org (gdb) x/2hx 0x800005cc 0x800005cc: 0xf200 0x0808 This patch adds the instruction. Bug: https://bugs.launchpad.net/qemu/+bug/1881450 Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200531131951.631902-1-laurent@vivier.eu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-03-13target/m68k: implement fcoshLaurent Vivier1-0/+1
Using a local m68k floatx80_cosh() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180312202728.23790-12-laurent@vivier.eu>
2018-03-13target/m68k: implement fsinhLaurent Vivier1-0/+1
Using a local m68k floatx80_sinh() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180312202728.23790-11-laurent@vivier.eu>
2018-03-13target/m68k: implement ftanhLaurent Vivier1-0/+1
Using local m68k floatx80_tanh() and floatx80_etoxm1() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180312202728.23790-10-laurent@vivier.eu>
2018-03-13target/m68k: implement fatanhLaurent Vivier1-0/+1
Using a local m68k floatx80_atanh() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180312202728.23790-9-laurent@vivier.eu>
2018-03-13target/m68k: implement facosLaurent Vivier1-0/+1
Using a local m68k floatx80_acos() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180312202728.23790-8-laurent@vivier.eu>
2018-03-13target/m68k: implement fasinLaurent Vivier1-0/+1
Using a local m68k floatx80_asin() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180312202728.23790-7-laurent@vivier.eu>
2018-03-13target/m68k: implement fatanLaurent Vivier1-0/+1
Using a local m68k floatx80_atan() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180312202728.23790-6-laurent@vivier.eu>
2018-03-13target/m68k: implement fsincosLaurent Vivier1-0/+1
using floatx80_sin() and floatx80_cos() Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180312202728.23790-5-laurent@vivier.eu>
2018-03-13target/m68k: implement fcosLaurent Vivier1-0/+1
Using a local m68k floatx80_cos() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180312202728.23790-4-laurent@vivier.eu>
2018-03-13target/m68k: implement fsinLaurent Vivier1-0/+1
Using a local m68k floatx80_sin() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180312202728.23790-3-laurent@vivier.eu>
2018-03-13target/m68k: implement ftanLaurent Vivier1-0/+1
Using a local m68k floatx80_tan() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180312202728.23790-2-laurent@vivier.eu>
2018-03-09target/m68k: implement ftentoxLaurent Vivier1-0/+1
Using a local m68k floatx80_tentox() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180305203910.10391-9-laurent@vivier.eu>
2018-03-09target/m68k: implement ftwotoxLaurent Vivier1-0/+1
Using a local m68k floatx80_twotox() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180305203910.10391-8-laurent@vivier.eu>
2018-03-09target/m68k: implement fetoxLaurent Vivier1-0/+1
Using a local m68k floatx80_etox() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180305203910.10391-7-laurent@vivier.eu>
2018-03-09target/m68k: implement flog2Laurent Vivier1-0/+1
Using a local m68k floatx80_log2() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180305203910.10391-6-laurent@vivier.eu>
2018-03-09target/m68k: implement flog10Laurent Vivier1-0/+1
Using a local m68k floatx80_log10() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180305203910.10391-5-laurent@vivier.eu>
2018-03-09target/m68k: implement flognLaurent Vivier1-0/+1
Using a local m68k floatx80_logn() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180305203910.10391-4-laurent@vivier.eu>
2018-03-09target/m68k: implement flognp1Laurent Vivier1-0/+1
Using a local m68k floatx80_lognp1() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20180305203910.10391-3-laurent@vivier.eu>
2018-03-04target/m68k: add fscale, fgetman and fgetexpLaurent Vivier1-0/+3
Using local m68k floatx80_getman(), floatx80_getexp(), floatx80_scale() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180224201802.911-5-laurent@vivier.eu>
2018-03-04target/m68k: add fmod/fremLaurent Vivier1-0/+2
Using a local m68k floatx80_mod() [copied from previous: Written by Andreas Grabher for Previous, NeXT Computer Emulator.] The quotient byte of the FPSR is updated with the result of the operation. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180224201802.911-3-laurent@vivier.eu>
2018-01-25target/m68k: add pflush/ptestLaurent Vivier1-0/+2
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180118193846.24953-7-laurent@vivier.eu>
2018-01-04target/m68k: add the Interrupt Stack PointerLaurent Vivier1-1/+3
Add the third stack pointer, the Interrupt Stack Pointer (ISP) (680x0 only). This stack will be needed in softmmu mode. Update movec to set/get the value of the three stacks. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-17-laurent@vivier.eu>
2018-01-04target/m68k: add resetLaurent Vivier1-0/+4
The instruction traps if the CPU is not in Supervisor state but the helper is empty because there is no easy way to reset all the peripherals without resetting the CPU itself. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-12-laurent@vivier.eu>
2018-01-04target/m68k: add chk and chk2Laurent Vivier1-0/+3
chk and chk2 compare a value to boundaries, and trigger a CHK exception if the value is out of bounds. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180104012913.30763-8-laurent@vivier.eu>
2017-10-24target/m68k: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota1-0/+1
Thereby decoupling the resulting translated code from the current state of the system. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-06-29target/m68k: add fmovemLaurent Vivier1-0/+6
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170628204241.32106-8-laurent@vivier.eu>
2017-06-29target/m68k: add explicit single and double precision operations (part 2)Laurent Vivier1-1/+7
Add fsabs, fdabs, fsneg, fdneg, fsmove and fdmove. The value is converted using the new floatx80_round() function. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170628204241.32106-7-laurent@vivier.eu>
2017-06-29target/m68k: add fsglmul and fsgldivLaurent Vivier1-0/+2
fsglmul and fsgldiv truncate data to single precision before computing results. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170628204241.32106-6-laurent@vivier.eu>
2017-06-29target/m68k: add explicit single and double precision operationsLaurent Vivier1-0/+10
Add fssqrt, fdsqrt, fsadd, fdadd, fssub, fdsub, fsmul, fdmul, fsdiv, fddiv. The precision is managed using set_floatx80_rounding_precision(). Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170628204241.32106-4-laurent@vivier.eu>
2017-06-29target/m68k: add fmovecrLaurent Vivier1-0/+1
fmovecr moves a floating point constant from the FPU ROM to a floating point register. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20170628204241.32106-3-laurent@vivier.eu>
2017-06-21target-m68k: add FPCR and FPSRLaurent Vivier1-2/+3
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170620205121.26515-6-laurent@vivier.eu>
2017-06-21target-m68k: use floatx80 internallyLaurent Vivier1-15/+22
Coldfire uses float64, but 680x0 use floatx80. This patch introduces the use of floatx80 internally and enables 680x0 80bits FPU. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170620205121.26515-4-laurent@vivier.eu>
2017-01-14target-m68k: Implement bfffoRichard Henderson1-0/+3
Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1479242669-25852-1-git-send-email-rth@twiddle.net> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-01-14target-m68k: Implement bitfield ops for memoryRichard Henderson1-0/+7
Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1478699171-10637-6-git-send-email-rth@twiddle.net> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2016-12-27target-m68k: Inline shiftsRichard Henderson1-3/+0
Also manage word and byte operands and fix the computation of overflow in the case of M68000 arithmetic shifts. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1478699171-10637-4-git-send-email-rth@twiddle.net>
2016-12-27target-m68k: add cas/cas2 opsLaurent Vivier1-0/+2
Implement CAS using cmpxchg. Implement CAS2 using helper and either cmpxchg when the 32bit addresses are consecutive, or with parallel_cpus+cpu_loop_exit_atomic() otherwise. Suggested-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-12-27target-m68k: add 680x0 divu/divs variantsLaurent Vivier1-2/+6
Update helper to set the throwing location in case of div-by-0. Cleanup divX.w and add quad word variants of divX.l. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twidle.net> [laurent: modified to clear Z on overflow, as found with risu]
2016-12-20Move target-* CPU file into a target/ folderThomas Huth1-0/+49
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
generated by cgit v1.1 at 2024-10-01 16:53:41 +0000