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2024-04-24target/m68k: Perform the semihosting test during translateRichard Henderson1-1/+1
Replace EXCP_HALT_INSN by EXCP_SEMIHOSTING. Perform the pre- and post-insn tests during translate, leaving only the actual semihosting operation for the exception. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-04-09target/m68k: Map FPU exceptions to FPSR registerKeith Packard1-1/+2
Add helpers for reading/writing the 68881 FPSR register so that changes in floating point exception state can be seen by the application. Call these helpers in pre_load/post_load hooks to synchronize exception state. Signed-off-by: Keith Packard <keithp@keithp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230803035231.429697-1-keithp@keithp.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-23target/m68k: Fix exception frame format for 68010Daniel Palmer1-0/+2
From the 68010 a word with the frame format and exception vector are placed on the stack before the PC and SR. M68K_FEATURE_QUAD_MULDIV is currently checked to workout if to do this or not for the configured CPU but that flag isn't set for 68010 so currently the exception stack when 68010 is configured is incorrect. It seems like checking M68K_FEATURE_MOVEFROMSR_PRIV would do but adding a new flag that shows exactly what is going on here is maybe clearer. Add a new flag for the behaviour, M68K_FEATURE_EXCEPTION_FORMAT_VEC, and set it for 68010 and above, and then use it to control if the format and vector word are pushed/pop during exception entry/exit. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2164 Signed-off-by: Daniel Palmer <daniel@0x0f.com> Message-ID: <20240115101643.2165387-1-daniel@0x0f.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-02-21m68k: correct typosManos Pitsidianakis1-3/+4
Correct typos automatically found with the `typos` tool <https://crates.io/crates/typos> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> (mjt: trivial fixup "covers" suggested by Thomas) Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-02-03include/exec: Implement cpu_mmu_index genericallyRichard Henderson1-4/+0
For user-only mode, use MMU_USER_IDX. For system mode, use CPUClass.mmu_index. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-05target/m68k: Use generic cpu_list()Gavin Shan1-4/+0
Before it's applied: [gshan@gshan q]$ ./build/qemu-system-m68k -cpu ? cfv4e m5206 m5208 m68000 m68010 m68020 m68030 m68040 m68060 any After it's applied: [gshan@gshan q]$ ./build/qemu-system-m68k -cpu ? Available CPUs: any cfv4e m5206 m5208 m68000 m68010 m68020 m68030 m68040 m68060 Signed-off-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20231114235628.534334-15-gshan@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-11-07target: Move ArchCPUClass definition to 'cpu.h'Philippe Mathieu-Daudé1-0/+13
The OBJECT_DECLARE_CPU_TYPE() macro forward-declares each ArchCPUClass type. These forward declarations are sufficient for code in hw/ to use the QOM definitions. No need to expose these structure definitions. Keep each local to their target/ by moving them to the corresponding "cpu.h" header. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231013140116.255-13-philmd@linaro.org>
2023-11-07target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'Philippe Mathieu-Daudé1-2/+0
Hegerogeneous code needs access to the FOO_CPU_TYPE_NAME() macro to resolve target CPU types. Move the declaration (along with the required FOO_CPU_TYPE_SUFFIX) to "cpu-qom.h". "target/foo/cpu-qom.h" is supposed to be target agnostic (include-able by any target). Add such mention in the header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231013140116.255-7-philmd@linaro.org>
2023-11-07target: Unify QOM stylePhilippe Mathieu-Daudé1-2/+0
Enforce the style described by commit 067109a11c ("docs/devel: mention the spacing requirement for QOM"): The first declaration of a storage or class structure should always be the parent and leave a visual space between that declaration and the new code. It is also useful to separate backing for properties (options driven by the user) and internal state to make navigation easier. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20231013140116.255-2-philmd@linaro.org>
2023-10-03accel/tcg: Move CPUNegativeOffsetState into CPUStateRichard Henderson1-1/+0
Retain the separate structure to emphasize its importance. Enforce CPUArchState always follows CPUState without padding. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-26target: Widen pc/cs_base in cpu_get_tb_cpu_stateAnton Johansson1-2/+2
Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230621135633.1649-4-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-02-27target/cpu: Restrict do_transaction_failed() handlers to sysemuPhilippe Mathieu-Daudé1-0/+2
The 'hwaddr' type is only available / meaningful on system emulation. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221216215519.5522-6-philmd@linaro.org>
2023-02-27target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemuPhilippe Mathieu-Daudé1-1/+1
The 'hwaddr' type is only available / meaningful on system emulation. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221216215519.5522-5-philmd@linaro.org>
2022-09-26target/m68k: use M68K_FEATURE_MOVEFROMSR_PRIV feature for move_from_sr ↵Mark Cave-Ayland1-0/+2
privilege check Now that M68K_FEATURE_M68000 has been renamed to M68K_FEATURE_M68K it is easier to see that the privilege exception check is wrong: it is currently only generated for ColdFire CPUs when in fact it should also be generated for Motorola CPUs from the 68010 onwards. Introduce a new M68K_FEATURE_MOVEFROMSR_PRIV feature which is set for all non- Motorola CPUs, and for all Motorola CPUs from the 68010 onwards and use it to determine whether a privilege exception should be generated for the MOVE-from-SR instruction. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220925134804.139706-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-09-26target/m68k: increase size of m68k CPU features from uint32_t to uint64_tMark Cave-Ayland1-3/+3
There are already 32 feature bits in use, so change the size of the m68k CPU features to uint64_t (along with the associated m68k_feature() functions) to allow up to 64 feature bits to be used. At the same time make use of the BIT_ULL() macro when reading/writing the CPU feature bits to improve readability, and also update m68k_feature() to return a bool rather than an int. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220925134804.139706-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-09-21target/m68k: rename M68K_FEATURE_M68000 to M68K_FEATURE_M68KMark Cave-Ayland1-2/+3
The M68K_FEATURE_M68000 feature is misleading in that its name suggests the feature is defined just for Motorola 68000 CPUs, whilst in fact it is defined for all Motorola 680X0 CPUs. In order to avoid confusion with the other M68K_FEATURE_M680X0 constants which define the features available for specific Motorola CPU models, rename M68K_FEATURE_M68000 to M68K_FEATURE_M68K and add comments to clarify its usage. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220917112515.83905-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-06-02target/m68k: Implement TRAPccRichard Henderson1-0/+2
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/754 Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220602013401.303699-11-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-06-02target/m68k: Fix address argument for EXCP_CHKRichard Henderson1-0/+6
According to the M68040 Users Manual, section 8.4.3, Six word stack frame (format 2), CHK, CHK2 (and others) are supposed to record the next insn in PC and the address of the trapping instruction in ADDRESS. Create a raise_exception_format2 function to centralize recording of the trapping pc in mmu.ar, plus advancing to the next insn. Update m68k_interrupt_all to pass mmu.ar to do_stack_frame. Update cpu_loop to pass mmu.ar to siginfo.si_addr, as the kernel does in trap_c(). Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220602013401.303699-7-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2022-04-06Move CPU softfloat unions to cpu-float.hMarc-André Lureau1-0/+1
The types are no longer used in bswap.h since commit f930224fffe ("bswap.h: Remove unused float-access functions"), there isn't much sense in keeping it there and having a dependency on fpu/. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20220323155743.1585078-29-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-03-06target: Use ArchCPU as interface to target CPUPhilippe Mathieu-Daudé1-1/+1
ArchCPU is our interface with target-specific code. Use it as a forward-declared opaque pointer (abstract type), having its structure defined by each target. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220214183144.27402-15-f4bug@amsat.org>
2022-03-06target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macroPhilippe Mathieu-Daudé1-2/+0
Replace the boilerplate code to declare CPU QOM types and macros, and forward-declare the CPU instance type. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220214183144.27402-14-f4bug@amsat.org>
2022-03-06target: Use CPUArchState as interface to target-specific CPU statePhilippe Mathieu-Daudé1-2/+1
While CPUState is our interface with generic code, CPUArchState is our interface with target-specific code. Use CPUArchState as an abstract type, defined by each target. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220214183144.27402-13-f4bug@amsat.org>
2021-09-21include/exec: Move cpu_signal_handler declarationRichard Henderson1-8/+0
There is nothing target specific about this. The implementation is host specific, but the declaration is 100% common. Reviewed-By: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-14target/m68k: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé1-0/+2
Restrict cpu_exec_interrupt() and its callees to sysemu. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210911165434.531552-13-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26target/m68k: implement m68k "any instruction" trace modeMark Cave-Ayland1-0/+8
The m68k trace mode is controlled by the top 2 bits in the SR register. Implement the m68k "any instruction" trace mode where bit T1=1 and bit T0=0 in which the CPU generates an EXCP_TRACE exception (vector 9 or offset 0x24) after executing each instruction. This functionality is used by the NetBSD kernel debugger to allow single-stepping on m68k architectures. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210519142917.16693-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-03-11target/m68k: add M68K_FEATURE_UNALIGNED_DATA featureMark Cave-Ayland1-0/+2
According to the M68040UM Appendix D the requirement for data accesses to be word aligned is only for the 68000, 68008 and 68010 CPUs. Later CPUs from the 68020 onwards will allow unaligned data accesses but at the cost of being less efficient. Add a new M68K_FEATURE_UNALIGNED_DATA feature to specify that data accesses are not required to be word aligned, and don't perform the alignment on the stack pointer when taking an exception if this feature is not selected. This is required because the MacOS DAFB driver attempts to call an A-trap with a byte-aligned stack pointer during initialisation and without this the stack pointer is off by one when the A-trap returns. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210308121155.2476-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-03-11target/m68k: reformat m68k_features enumMark Cave-Ayland1-22/+44
Move the feature comment from after the feature name to the preceding line to allow for longer feature names and descriptions without hitting the 80 character line limit. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210308121155.2476-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-11m68k: add MSP detection support for stack pointer swap helpersLucien Murray-Pitts1-1/+8
On m68k there are two varities of stack pointers: USP with SSP or ISP/MSP. Only the 68020/30/40 support the MSP register the stack swap helpers don't support this feature. This patch adds this support, as well as comments to CPUM68KState to make it clear how stacks are handled Signed-off-by: Lucien Murray-Pitts <lucienmp.qemu@gmail.com> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <c61ad2d8b39f3b03b431819b6bf602a1c332b921.1612137712.git.balaton@eik.bme.hu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-11m68k: MOVEC insn. should generate exception if wrong CR is accessedLucien Murray-Pitts1-0/+1
Add CPU class detection for each CR type in the m68k_move_to/from helpers, so that it throws and exception if an unsupported register is requested for that CPU class. Reclassified MOVEC insn. as only supported from 68010. Signed-off-by: Lucien Murray-Pitts <lucienmp.qemu@gmail.com> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <fc0d0187478716f05d990949347071969b743151.1612137712.git.balaton@eik.bme.hu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-11m68k: add missing BUSCR/PCR CR defines, and BUSCR/PCR/CAAR CR to ↵Lucien Murray-Pitts1-0/+4
m68k_move_to/from The BUSCR/PCR CR defines were missing for 68060, and the move_to/from helper functions were also missing a decode for the 68060 M68K_CR_CAAR CR register. Added missing defines, and respective decodes for all three CR registers to the helpers. Although this patch defines them, the implementation is empty in this patch and these registers will result in a cpu abort - which is the default prior to this patch. This patch aims to reach full coverage of all CR registers within the helpers. Signed-off-by: Lucien Murray-Pitts <lucienmp.qemu@gmail.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <19e5c0fa8baed6479ed0502fd3deb132d19457fb.1612137712.git.balaton@eik.bme.hu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-11m68k: cascade m68k_features by m680xx_cpu_initfn() to improve readabilityLucien Murray-Pitts1-0/+1
The m680XX_cpu_initfn functions have been rearranged to cascade starting from the base 68000, so that the 68010 then inherits from this, and so on until the 68060. This makes it simpler to track features since in most cases the m68k were product enhancements on each other, with only a few instructions being retired. Because each cpu class inherits the previous CPU class, then for example the 68020 also has the feature 68010, and 68000 and so on upto the 68060. - Added 68010 cpu class, and moved correct features into 68000/68010. - Added m68k_unset_feature to allow removing a feature in the inheritence Signed-off-by: Lucien Murray-Pitts <lucienmp.qemu@gmail.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <c652fe7537f8b4fe87a13ecbbc0ea751fb71532f.1612137712.git.balaton@eik.bme.hu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-02-11m68k: improve cpu instantiation commentsLucien Murray-Pitts1-20/+29
Improvement in comments for the instantiation functions. This is to highlight what each cpu class, in the 68000 series, contains in terms of instructions/features. Signed-off-by: Lucien Murray-Pitts <lucienmp.qemu@gmail.com> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <2dfe32672ee6ddce4b54c6bcfce579d35abeaf51.1612137712.git.balaton@eik.bme.hu> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2020-12-12target/m68k: Add vmstate definition for M68kCPULaurent Vivier1-0/+1
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20201022203000.1922749-3-laurent@vivier.eu>
2020-12-12target/m68k: remove useless qregs arrayLaurent Vivier1-4/+0
They are unused since the target has been converted to TCG. Fixes: e1f3808e03f7 ("Convert m68k target to TCG.") Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20201022203000.1922749-2-laurent@vivier.eu>
2020-03-17gdbstub: extend GByteArray to read register helpersAlex Bennée1-1/+1
Instead of passing a pointer to memory now just extend the GByteArray to all the read register helpers. They can then safely append their data through the normal way. We don't bother with this abstraction for write registers as we have already ensured the buffer being copied from is the correct size. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-Id: <20200316172155.971-15-alex.bennee@linaro.org>
2020-01-15target/m68k: Use cpu_*_mmuidx_ra instead of MMU_MODE{0,1}_SUFFIXRichard Henderson1-2/+0
The generated *_user functions are unused. The *_kernel functions have a couple of users in op_helper.c; use *_mmuidx_ra instead, with MMU_KERNEL_IDX. Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Use *_mmuidx_ra directly, without intermediate macros.
2020-01-07target/m68k: only change valid bits in CACRLaurent Vivier1-1/+4
This is used by netBSD (and MacOS ROM) to detect the MMU type Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Message-Id: <20191220172415.35838-1-laurent@vivier.eu> [lv: add a comment before m680x0_cpu_common()] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-06-26m68k comments break patch submission due to being incorrectly formattedLucien Murray-Pitts1-11/+18
Altering all comments in target/m68k to match Qemu coding styles so that future patches wont fail due to style breaches. Signed-off-by: Lucien Murray-Pitts <lucienmp.qemu@gmail.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20190606234125.GA4830@localhost.localdomain> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-06-12Include qemu-common.h exactly where neededMarkus Armbruster1-1/+0
No header includes qemu-common.h after this commit, as prescribed by qemu-common.h's file comment. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190523143508.25387-5-armbru@redhat.com> [Rebased with conflicts resolved automatically, except for include/hw/arm/xlnx-zynqmp.h hw/arm/nrf51_soc.c hw/arm/msf2-soc.c block/qcow2-refcount.c block/qcow2-cluster.c block/qcow2-cache.c target/arm/cpu.h target/lm32/cpu.h target/m68k/cpu.h target/mips/cpu.h target/moxie/cpu.h target/nios2/cpu.h target/openrisc/cpu.h target/riscv/cpu.h target/tilegx/cpu.h target/tricore/cpu.h target/unicore32/cpu.h target/xtensa/cpu.h; bsd-user/main.c and net/tap-bsd.c fixed up]
2019-06-10cpu: Remove CPU_COMMONRichard Henderson1-2/+0
This macro is now always empty, so remove it. This leaves the entire contents of CPUArchState under the control of the guest architecture. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-10cpu: Introduce CPUNegativeOffsetStateRichard Henderson1-0/+1
Nothing in there so far, but all of the plumbing done within the target ArchCPU state. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-10cpu: Move ENV_OFFSET to exec/gen-icount.hRichard Henderson1-1/+0
Now that we have ArchCPU, we can define this generically, in the one place that needs it. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-10target/m68k: Use env_cpuRichard Henderson1-5/+0
Cleanup in the boilerplate that each target must define. The combination CPU(m68k_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Acked-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-10cpu: Replace ENV_GET_CPU with env_cpuRichard Henderson1-2/+0
Now that we have both ArchCPU and CPUArchState, we can define this generically instead of via macro in each target's cpu.h. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-10cpu: Define ArchCPURichard Henderson1-0/+1
For all targets, do this just before including exec/cpu-all.h. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-10cpu: Define CPUArchState with typedefRichard Henderson1-2/+2
For all targets, do this just before including exec/cpu-all.h. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-10tcg: Split out target/arch/cpu-param.hRichard Henderson1-14/+2
For all targets, into this new file move TARGET_LONG_BITS, TARGET_PAGE_BITS, TARGET_PHYS_ADDR_SPACE_BITS, TARGET_VIRT_ADDR_SPACE_BITS, and NB_MMU_MODES. Include this new file from exec/cpu-defs.h. This now removes the somewhat odd requirement that target/arch/cpu.h defines TARGET_LONG_BITS before including exec/cpu-defs.h, so push the bulk of the includes within target/arch/cpu.h to the top. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-05-17Merge remote-tracking branch 'remotes/vivier/tags/m68k-staging-pull-request' ↵Peter Maydell1-3/+4
into staging code cleanup, switch to transaction_failed hook # gpg: Signature made Thu 16 May 2019 23:33:00 BST # gpg: using RSA key F30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/m68k-staging-pull-request: target/m68k: Optimize rotate_x() using extract_i32() target/m68k: Fix a tcg_temp leak target/m68k: Reduce the l1 TCGLabel scope target/m68k: Switch to transaction_failed hook target/m68k: In get_physical_address() check for memory access failures target/m68k: In dump_address_map() check for memory access failures Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # target/m68k/cpu.h
2019-05-16target/m68k: Switch to transaction_failed hookPeter Maydell1-3/+4
Switch the m68k target from the old unassigned_access hook to the transaction_failed hook. The notable difference is that rather than it being called for all physical memory accesses which fail (including those made by DMA devices or by the gdbstub), it is only called for those made by the CPU via its MMU. (In previous commits we put in explicit checks for the direct physical loads made by the target/m68k code which will no longer be handled by calling the unassigned_access hook.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20181210165636.28366-4-peter.maydell@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2019-05-10target/m68k: Convert to CPUClass::tlb_fillRichard Henderson1-2/+3
Cc: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2025-02-06 19:29:25 +0000