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AgeCommit message (Expand)AuthorFilesLines
2023-05-06target/loongarch: Implement vldiSong Gao1-0/+4
2023-05-06target/loongarch: Implement vld vstSong Gao1-0/+36
2023-05-06target/loongarch: Implement vilvl vilvh vextrins vshufSong Gao1-0/+25
2023-05-06target/loongarch: Implement vreplve vpack vpickSong Gao1-0/+34
2023-05-06target/loongarch: Implement vinsgr2vr vpickve2gr vreplgr2vrSong Gao1-0/+30
2023-05-06target/loongarch: Implement vbitsel vsetSong Gao1-0/+17
2023-05-06target/loongarch: Implement vfcmpSong Gao1-0/+5
2023-05-06target/loongarch: Implement vseq vsle vsltSong Gao1-0/+43
2023-05-06target/loongarch: Implement LSX fpu fcvt instructionsSong Gao1-0/+56
2023-05-06target/loongarch: Implement LSX fpu arith instructionsSong Gao1-0/+43
2023-05-06target/loongarch: Implement vfrstpSong Gao1-0/+5
2023-05-06target/loongarch: Implement vbitclr vbitset vbitrevSong Gao1-0/+25
2023-05-06target/loongarch: Implement vpcntSong Gao1-0/+5
2023-05-06target/loongarch: Implement vclo vclzSong Gao1-0/+9
2023-05-06target/loongarch: Implement vssrlrn vssrarnSong Gao1-0/+30
2023-05-06target/loongarch: Implement vssrln vssranSong Gao1-0/+30
2023-05-06target/loongarch: Implement vsrlrn vsrarnSong Gao1-0/+16
2023-05-06target/loongarch: Implement vsrln vsranSong Gao1-0/+17
2023-05-06target/loongarch: Implement vsrlr vsrarSong Gao1-0/+18
2023-05-06target/loongarch: Implement vsllwil vextlSong Gao1-0/+9
2023-05-06target/loongarch: Implement vsll vsrl vsra vrotrSong Gao1-0/+36
2023-05-06target/loongarch: Implement LSX logic instructionsSong Gao1-0/+13
2023-05-06target/loongarch: Implement vmskltz/vmskgez/vmsknzSong Gao1-0/+7
2023-05-06target/loongarch: Implement vsigncovSong Gao1-0/+5
2023-05-06target/loongarch: Implement vexthSong Gao1-0/+9
2023-05-06target/loongarch: Implement vsatSong Gao1-0/+12
2023-05-06target/loongarch: Implement vdiv/vmodSong Gao1-0/+17
2023-05-06target/loongarch: Implement vmadd/vmsub/vmaddw{ev/od}Song Gao1-0/+34
2023-05-06target/loongarch: Implement vmul/vmuh/vmulw{ev/od}Song Gao1-0/+38
2023-05-06target/loongarch: Implement vmax/vminSong Gao1-0/+35
2023-05-06target/loongarch: Implement vaddaSong Gao1-0/+5
2023-05-06target/loongarch: Implement vabsdSong Gao1-0/+9
2023-05-06target/loongarch: Implement vavg/vavgrSong Gao1-0/+17
2023-05-06target/loongarch: Implement vaddw/vsubwSong Gao1-0/+43
2023-05-06target/loongarch: Implement vhaddw/vhsubwSong Gao1-0/+17
2023-05-06target/loongarch: Implement vsadd/vssubSong Gao1-0/+17
2023-05-06target/loongarch: Implement vnegSong Gao1-0/+7
2023-05-06target/loongarch: Implement vaddi/vsubiSong Gao1-0/+11
2023-05-06target/loongarch: Implement vadd/vsubSong Gao1-0/+22
2023-01-23target/loongarch: Disassemble jirl properlyRichard Henderson1-1/+2
2022-06-06target/loongarch: Add timer related instructions support.Xiaojuan Yang1-0/+3
2022-06-06target/loongarch: Add other core instructions supportXiaojuan Yang1-0/+11
2022-06-06target/loongarch: Add TLB instruction supportXiaojuan Yang1-0/+11
2022-06-06target/loongarch: Add LoongArch IOCSR instructionXiaojuan Yang1-0/+9
2022-06-06target/loongarch: Add LoongArch CSR instructionXiaojuan Yang1-0/+13
2022-06-06target/loongarch: Add branch instruction translationSong Gao1-0/+28
2022-06-06target/loongarch: Add floating point load/store instruction translationSong Gao1-0/+24
2022-06-06target/loongarch: Add floating point move instruction translationSong Gao1-0/+37
2022-06-06target/loongarch: Add floating point conversion instruction translationSong Gao1-0/+32
2022-06-06target/loongarch: Add floating point comparison instruction translationSong Gao1-0/+8
generated by cgit v1.1 at 2024-12-23 12:24:43 +0000