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AgeCommit message (Expand)AuthorFilesLines
2023-05-06target/loongarch: Use {set/get}_gpr replace to cpu_fprSong Gao4-37/+115
2023-05-06target/loongarch: Implement vldiSong Gao1-0/+137
2023-05-06target/loongarch: Implement vld vstSong Gao1-0/+159
2023-05-06target/loongarch: Implement vilvl vilvh vextrins vshufSong Gao1-0/+25
2023-05-06target/loongarch: Implement vreplve vpack vpickSong Gao1-0/+144
2023-05-06target/loongarch: Implement vinsgr2vr vpickve2gr vreplgr2vrSong Gao1-0/+110
2023-05-06target/loongarch: Implement vbitsel vsetSong Gao1-0/+74
2023-05-06target/loongarch: Implement vfcmpSong Gao1-0/+32
2023-05-06target/loongarch: Implement vseq vsle vsltSong Gao1-0/+185
2023-05-06target/loongarch: Implement LSX fpu fcvt instructionsSong Gao1-0/+56
2023-05-06target/loongarch: Implement LSX fpu arith instructionsSong Gao1-0/+55
2023-05-06target/loongarch: Implement vfrstpSong Gao1-0/+5
2023-05-06target/loongarch: Implement vbitclr vbitset vbitrevSong Gao1-0/+305
2023-05-06target/loongarch: Implement vpcntSong Gao1-0/+5
2023-05-06target/loongarch: Implement vclo vclzSong Gao1-0/+9
2023-05-06target/loongarch: Implement vssrlrn vssrarnSong Gao1-0/+30
2023-05-06target/loongarch: Implement vssrln vssranSong Gao1-0/+30
2023-05-06target/loongarch: Implement vsrlrn vsrarnSong Gao1-0/+16
2023-05-06target/loongarch: Implement vsrln vsranSong Gao1-0/+16
2023-05-06target/loongarch: Implement vsrlr vsrarSong Gao1-0/+18
2023-05-06target/loongarch: Implement vsllwil vextlSong Gao1-0/+21
2023-05-06target/loongarch: Implement vsll vsrl vsra vrotrSong Gao1-0/+36
2023-05-06target/loongarch: Implement LSX logic instructionsSong Gao1-0/+56
2023-05-06target/loongarch: Implement vmskltz/vmskgez/vmsknzSong Gao1-0/+7
2023-05-06target/loongarch: Implement vsigncovSong Gao1-0/+53
2023-05-06target/loongarch: Implement vexthSong Gao1-0/+20
2023-05-06target/loongarch: Implement vsatSong Gao1-0/+101
2023-05-06target/loongarch: Implement vdiv/vmodSong Gao1-0/+17
2023-05-06target/loongarch: Implement vmadd/vmsub/vmaddw{ev/od}Song Gao1-0/+612
2023-05-06target/loongarch: Implement vmul/vmuh/vmulw{ev/od}Song Gao1-0/+550
2023-05-06target/loongarch: Implement vmax/vminSong Gao1-0/+200
2023-05-06target/loongarch: Implement vaddaSong Gao1-0/+53
2023-05-06target/loongarch: Implement vabsdSong Gao1-0/+95
2023-05-06target/loongarch: Implement vavg/vavgrSong Gao1-0/+197
2023-05-06target/loongarch: Implement vaddw/vsubwSong Gao1-0/+795
2023-05-06target/loongarch: Implement vhaddw/vhsubwSong Gao1-0/+17
2023-05-06target/loongarch: Implement vsadd/vssubSong Gao1-0/+17
2023-05-06target/loongarch: Implement vnegSong Gao1-0/+20
2023-05-06target/loongarch: Implement vaddi/vsubiSong Gao1-0/+37
2023-05-06target/loongarch: Implement vadd/vsubSong Gao1-0/+69
2023-05-06target/loongarch: Add CHECK_SXE maccro for check LSX enableSong Gao1-0/+11
2023-05-06target/loongarch: meson.build support build LSXSong Gao1-0/+5
2023-03-05target/loongarch: Drop tcg_temp_freeRichard Henderson9-99/+6
2023-03-05target/loongarch: Drop temp_newRichard Henderson1-1/+1
2023-01-23target/loongarch: Disassemble jirl properlyRichard Henderson1-1/+1
2022-11-07target/loongarch: Fix return value of CHECK_FPERui Wang1-1/+1
2022-11-07target/loongarch: Separate the hardware flags into MMU index and PLVRui Wang1-2/+2
2022-11-04target/loongarch: Fix emulation of float-point disable exceptionRui Wang4-11/+93
2022-11-04target/loongarch: Adjust the layout of hardware flags bit fieldsRui Wang1-1/+1
2022-10-17target/loongarch: Fix fnm{sub/add}_{s/d} set wrong flagsSong Gao1-6/+6
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