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AgeCommit message (Expand)AuthorFilesLines
2022-05-14target/i386: Support Arch LBR in CPUID enumerationYang Weijiang1-1/+19
2022-05-14target/i386: introduce helper to access supported CPUIDPaolo Bonzini1-16/+25
2022-05-14target/i386: Enable Arch LBR migration states in vmstateYang Weijiang1-0/+38
2022-05-14target/i386: Add MSR access interface for Arch LBRYang Weijiang2-0/+77
2022-05-14target/i386: Add XSAVES support for Arch LBRYang Weijiang2-1/+28
2022-05-14target/i386: Enable support for XSAVES based featuresYang Weijiang2-26/+92
2022-05-14target/i386: Add kvm_get_one_msr helperYang Weijiang1-20/+26
2022-05-14target/i386: Add lbr-fmt vPMU option to support guest LBRYang Weijiang2-0/+50
2022-05-14i386/cpu: Remove the deprecated cpu model 'Icelake-Client'Robert Hoo1-122/+0
2022-05-14WHPX: fixed TPR/CR8 translation issues affecting VM debuggingIvan Shcherbakov1-3/+10
2022-05-12target/i386: do not consult nonexistent host leavesPaolo Bonzini1-5/+36
2022-05-11Normalize header guard symbol definitionMarkus Armbruster1-1/+1
2022-05-11Clean up header guards that don't match their file nameMarkus Armbruster5-14/+14
2022-05-09disas: Remove old libopcode i386 disassemblerThomas Huth1-1/+0
2022-05-07WHPX: support for xcr0Sunil Muthuswamy2-0/+90
2022-04-28i386: pcmpestr 64-bit sign extension bugPaul Brook1-11/+9
2022-04-26target/i386: Suppress coverity warning on fsave/frstorRichard Henderson1-2/+2
2022-04-21compiler.h: replace QEMU_NORETURN with G_NORETURNMarc-André Lureau5-34/+36
2022-04-20Merge tag 'pull-log-20220420' of https://gitlab.com/rth7680/qemu into stagingRichard Henderson1-10/+12
2022-04-20exec/translator: Pass the locked filepointer to disas_log hookRichard Henderson1-3/+3
2022-04-20*: Use fprintf between qemu_log_trylock/unlockRichard Henderson1-6/+8
2022-04-20util/log: Rename qemu_log_lock to qemu_log_trylockRichard Henderson1-1/+1
2022-04-20target/i386: fix byte swap issue with XMM register accessAlex Bennée1-2/+2
2022-04-13target/i386: Remove unused XMMReg, YMMReg types and CPUState fieldsPeter Maydell1-18/+0
2022-04-13target/i386: do not access beyond the low 128 bits of SSE registersPaolo Bonzini1-28/+47
2022-04-06hw: hyperv: Initial commit for Synthetic Debugging deviceJon Doron1-0/+6
2022-04-06hyperv: Add support to process syndbg commandsJon Doron5-8/+135
2022-04-06hyperv: Add definitions for syndbgJon Doron1-0/+37
2022-04-06whpx: Added support for breakpoints and steppingIvan Shcherbakov4-14/+788
2022-04-06Remove qemu-common.h include from most unitsMarc-André Lureau15-15/+0
2022-04-06Move CPU softfloat unions to cpu-float.hMarc-André Lureau1-0/+1
2022-04-06Replace qemu_real_host_page variables with inlined functionsMarc-André Lureau3-13/+13
2022-04-06Replace config-time define HOST_WORDS_BIGENDIANMarc-André Lureau2-2/+2
2022-04-06qapi, target/i386/sev: Add cpu0-id to query-sev-capabilitiesDov Murik1-1/+41
2022-03-25Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell5-15/+35
2022-03-24target/i386: properly reset TSC on resetPaolo Bonzini2-1/+14
2022-03-24target/i386: tcg: high bits SSE cmp operation must be ignoredPaolo Bonzini1-4/+2
2022-03-23KVM: x86: workaround invalid CPUID[0xD,9] info on some AMD processorsPaolo Bonzini3-9/+16
2022-03-23i386: Set MCG_STATUS_RIPV bit for mce SRAR errorluofei1-1/+1
2022-03-23target/i386/kvm: Free xsave_buf when destroying vCPUPhilippe Mathieu-Daudé1-0/+2
2022-03-23target/i386: force maximum rounding precision for fildl[l]Alex Bennée1-0/+13
2022-03-21Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell1-4/+13
2022-03-21Use g_new() & friends where that makes obvious senseMarkus Armbruster5-8/+8
2022-03-20target/i386: kvm: do not access uninitialized variable on older kernelsPaolo Bonzini1-4/+13
2022-03-15Merge tag 'darwin-20220315' of https://github.com/philmd/qemu into stagingPeter Maydell7-56/+17
2022-03-15hvf: Remove deprecated hv_vcpu_flush() callsPhilippe Mathieu-Daudé3-5/+0
2022-03-15hvf: Make hvf_get_segments() / hvf_put_segments() localPhilippe Mathieu-Daudé2-4/+2
2022-03-15hvf: Use standard CR0 and CR4 register definitionsCameron Esfahani5-47/+15
2022-03-15KVM: SVM: always set MSR_AMD64_TSC_RATIO to default valueMaxim Levitsky1-3/+1
2022-03-15i386: Add Icelake-Server-v6 CPU model with 5-level EPT supportVitaly Kuznetsov1-0/+8
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