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2023-06-28accel: Fix a leak on Windows HAXPhilippe Mathieu-Daudé1-0/+3
2023-06-28accel: Remove unused hThread variable on TCG/WHPXPhilippe Mathieu-Daudé1-3/+0
2023-06-28accel: Re-enable WHPX cross-build on case sensitive filesystemsPhilippe Mathieu-Daudé2-4/+4
2023-06-26target: Widen pc/cs_base in cpu_get_tb_cpu_stateAnton Johansson1-2/+2
2023-06-26target/i386: implement SYSCALL/SYSRET in 32-bit emulatorsPaolo Bonzini6-13/+11
2023-06-26target/i386: implement RDPID in TCGPaolo Bonzini4-13/+44
2023-06-26target/i386: sysret and sysexit are privilegedPaolo Bonzini1-2/+2
2023-06-26target/i386: AMD only supports SYSENTER/SYSEXIT in 32-bit modePaolo Bonzini1-4/+6
2023-06-26target/i386: Intel only supports SYSCALL/SYSRET in long modePaolo Bonzini2-1/+12
2023-06-26target/i386: TCG supports WBNOINVDPaolo Bonzini2-2/+3
2023-06-26target/i386: TCG supports XSAVEERPTRPaolo Bonzini1-1/+3
2023-06-26target/i386: do not accept RDSEED if CPUID bit absentPaolo Bonzini1-0/+8
2023-06-26target/i386: TCG supports RDSEEDPaolo Bonzini1-3/+2
2023-06-26target/i386: TCG supports 3DNow! prefetch(w)Paolo Bonzini1-1/+2
2023-06-26target/i386: fix INVD vmexitPaolo Bonzini1-1/+1
2023-06-20meson: Replace softmmu_ss -> system_ssPhilippe Mathieu-Daudé7-14/+14
2023-06-20meson: Replace CONFIG_SOFTMMU -> CONFIG_SYSTEM_ONLYPhilippe Mathieu-Daudé1-1/+1
2023-06-20target/i386: Simplify i386_tr_init_disas_context()Philippe Mathieu-Daudé1-3/+0
2023-06-13target/i386: Rename helper template headers as '.h.inc'Philippe Mathieu-Daudé6-11/+11
2023-06-13target/i386/helper: Shuffle do_cpu_init()Philippe Mathieu-Daudé1-8/+4
2023-06-13target/i386/helper: Remove do_cpu_sipi() stub for user-mode emulationPhilippe Mathieu-Daudé2-4/+2
2023-06-06hvf: add guest debugging handlers for Apple Silicon hostsFrancesco Cagnin1-0/+9
2023-06-06hvf: add breakpoint handlersFrancesco Cagnin1-0/+24
2023-06-05accel/tcg: Introduce translator_io_startRichard Henderson1-42/+10
2023-06-05tcg: Add insn_start_words to TCGContextRichard Henderson1-1/+1
2023-06-05tcg: Pass TCGHelperInfo to tcg_gen_callNRichard Henderson1-0/+5
2023-06-05*: Add missing includes of tcg/tcg.hRichard Henderson1-0/+3
2023-05-25target/i386: EPYC-Rome model without XSAVESMaksim Davydov1-0/+10
2023-05-18target/i386: Fix exception classes for MOVNTPS/MOVNTPD.Ricky Zhou1-2/+3
2023-05-18target/i386: Fix exception classes for SSE/AVX instructions.Ricky Zhou1-23/+23
2023-05-18target/i386: Fix and add some comments next to SSE/AVX instructions.Ricky Zhou1-12/+12
2023-05-18target/i386: fix avx2 instructions vzeroall and vpermdqXinyu Li2-1/+9
2023-05-18target/i386: fix operand size for VCOMI/VUCOMI instructionsPaolo Bonzini1-2/+13
2023-05-18target/i386: add support for FB_CLEAR featureEmanuele Giuseppe Esposito2-1/+2
2023-05-18target/i386: add support for FLUSH_L1D featureEmanuele Giuseppe Esposito2-1/+3
2023-05-08target/i386: Add EPYC-Genoa model to support Zen 4 processor seriesBabu Moger1-0/+122
2023-05-08target/i386: Add VNMI and automatic IBRS feature bitsBabu Moger2-2/+5
2023-05-08target/i386: Add missing feature bits in EPYC-Milan modelBabu Moger1-0/+70
2023-05-08target/i386: Add feature bits for CPUID_Fn80000021_EAXBabu Moger2-0/+32
2023-05-08target/i386: Add a couple of feature bits in 8000_0008_EBXBabu Moger2-2/+6
2023-05-08target/i386: Add new EPYC CPU versions with updated cache_infoMichael Roth1-0/+118
2023-05-08target/i386: allow versioned CPUs to specify new cache_infoMichael Roth1-3/+32
2023-04-28target/i386: Add support for PREFETCHIT0/1 in CPUID enumerationJiaxi Chen2-1/+3
2023-04-28target/i386: Add support for AVX-NE-CONVERT in CPUID enumerationJiaxi Chen2-1/+3
2023-04-28target/i386: Add support for AVX-VNNI-INT8 in CPUID enumerationJiaxi Chen2-1/+25
2023-04-28target/i386: Add support for AVX-IFMA in CPUID enumerationJiaxi Chen2-1/+3
2023-04-28target/i386: Add support for AMX-FP16 in CPUID enumerationJiaxi Chen2-1/+3
2023-04-28target/i386: Add support for CMPCCXADD in CPUID enumerationJiaxi Chen2-1/+3
2023-04-28i386/cpu: Update how the EBX register of CPUID 0x8000001F is setTom Lendacky1-2/+2
2023-04-28i386/sev: Update checks and information related to reduced-phys-bitsTom Lendacky1-3/+14