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path: root/target/i386/translate.c
AgeCommit message (Expand)AuthorFilesLines
2018-11-27target/i386: Generate #UD when applying LOCK to a register destinationRichard Henderson1-15/+20
2018-10-30target/i386: Remove #ifdeffed-out icebp debugging hackPeter Maydell1-6/+0
2018-10-02target/i386: fix translation for icount modePavel Dovgalyuk1-3/+3
2018-10-02target/i386: rename HF_SVMI_MASK to HF_GUEST_MASKPaolo Bonzini1-2/+2
2018-10-02target/i386: move x86_64_hregs to DisasContextEmilio G. Cota1-153/+154
2018-10-02target/i386: move cpu_tmp1_i64 to DisasContextEmilio G. Cota1-80/+80
2018-10-02target/i386: move cpu_tmp3_i32 to DisasContextEmilio G. Cota1-32/+32
2018-10-02target/i386: move cpu_tmp2_i32 to DisasContextEmilio G. Cota1-173/+174
2018-10-02target/i386: move cpu_ptr1 to DisasContextEmilio G. Cota1-26/+26
2018-10-02target/i386: move cpu_ptr0 to DisasContextEmilio G. Cota1-49/+52
2018-10-02target/i386: move cpu_tmp4 to DisasContextEmilio G. Cota1-39/+39
2018-10-02target/i386: move cpu_tmp0 to DisasContextEmilio G. Cota1-138/+144
2018-10-02target/i386: move cpu_T1 to DisasContextEmilio G. Cota1-171/+170
2018-10-02target/i386: move cpu_T0 to DisasContextEmilio G. Cota1-580/+594
2018-10-02target/i386: move cpu_A0 to DisasContextEmilio G. Cota1-236/+236
2018-10-02target/i386: move cpu_cc_srcT to DisasContextEmilio G. Cota1-14/+18
2018-08-23fix "Missing break in switch" coverity reportsPaolo Bonzini1-0/+2
2018-06-28target-i386: Allow interrupt injection after STGIJan Kiszka1-1/+2
2018-06-28target/i386: Fix BLSR and BLSIRichard Henderson1-17/+9
2018-06-01tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson1-4/+4
2018-05-20tcg: fix s/compliment/complement/ typosEmilio G. Cota1-1/+1
2018-05-09translator: merge max_insns into DisasContextBaseEmilio G. Cota1-4/+1
2018-04-09Add missing bit for SSE instr in VEX decodingEugene Minibaev1-1/+3
2018-04-05target/i386: Fix andn instructionAlexandro Sanchez Bach1-1/+1
2017-12-29tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED*Richard Henderson1-7/+6
2017-12-21target/i386: Fix handling of VEX prefixesPeter Maydell1-1/+1
2017-12-21target/i386: Fix compiler warningsStefan Weil1-3/+4
2017-10-27Merge remote-tracking branch 'remotes/rth/tags/pull-dis-20171026' into stagingPeter Maydell1-7/+1
2017-10-25disas: Remove unused flags argumentsRichard Henderson1-1/+1
2017-10-25target/i386: Convert to disas_set_info hookRichard Henderson1-7/+1
2017-10-24tcg: Initialize cpu_env genericallyRichard Henderson1-3/+0
2017-10-24tcg: define tcg_init_ctx and make tcg_ctx a pointerEmilio G. Cota1-1/+1
2017-10-24target/i386: check CF_PARALLEL instead of parallel_cpusEmilio G. Cota1-2/+2
2017-10-24tcg: convert tb->cflags reads to tb_cflags(tb)Emilio G. Cota1-24/+24
2017-10-24qom: Introduce CPUClass.tcg_initializeRichard Henderson1-6/+0
2017-10-24tcg: Remove TCGV_EQUAL*Richard Henderson1-3/+3
2017-10-16target/i386: trap on instructions longer than >15 bytesPaolo Bonzini1-7/+22
2017-10-16target/i386: introduce x86_ld*_codePaolo Bonzini1-103/+125
2017-10-10tcg: remove addr argument from lookup_tb_ptrEmilio G. Cota1-12/+5
2017-10-09x86: Correct translation of some rdgsbase and wrgsbase encodingsTodd Eisenberger1-2/+2
2017-09-19target/i386: set rip_offset for further SSE instructionsJoseph Myers1-1/+2
2017-09-06target/i386: [tcg] Port to generic translation frameworkLluís Vilanova1-87/+19
2017-09-06target/i386: [tcg] Port to disas_logLluís Vilanova1-13/+19
2017-09-06target/i386: [tcg] Port to tb_stopLluís Vilanova1-12/+14
2017-09-06target/i386: [tcg] Port to translate_insnLluís Vilanova1-24/+42
2017-09-06target/i386: [tcg] Port to breakpoint_checkLluís Vilanova1-12/+34
2017-09-06target/i386: [tcg] Port to insn_startLluís Vilanova1-1/+8
2017-09-06target/i386: [tcg] Port to init_disas_contextLluís Vilanova1-19/+27
2017-09-06target/i386: [tcg] Port to DisasContextBaseLluís Vilanova1-71/+69
2017-09-06target: [tcg] Use a generic enum for DISAS_ valuesLluís Vilanova1-2/+1
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