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AgeCommit message (Expand)AuthorFilesLines
2021-10-15target/i386: Drop check for singlestep_enabledRichard Henderson2-11/+1
2021-10-15target/i386: Check CF_NO_GOTO_TB for dc->jmp_optRichard Henderson1-2/+3
2021-10-13target/i386: Use MO_128 for 16 byte atomicsRichard Henderson1-1/+1
2021-10-05tcg: Rename TCGMemOpIdx to MemOpIdxRichard Henderson1-2/+2
2021-09-14target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folderPhilippe Mathieu-Daudé2-64/+62
2021-09-14target/i386: Restrict cpu_exec_interrupt() handler to sysemuPhilippe Mathieu-Daudé3-9/+5
2021-09-14accel/tcg: Rename user-mode do_interrupt hack as fake_user_interruptPhilippe Mathieu-Daudé1-2/+4
2021-09-14target/i386: Simplify TARGET_X86_64 #ifdef'ryPhilippe Mathieu-Daudé1-3/+1
2021-09-14accel/tcg: Add DisasContextBase argument to translator_ld*Ilya Leoshkevich1-5/+5
2021-09-13target/i386: Added vVMLOAD and vVMSAVE featureLara Lazier2-1/+30
2021-09-13target/i386: Added changed priority check for VIRQLara Lazier2-15/+7
2021-09-13target/i386: Added ignore TPR check in ctl_has_irqLara Lazier1-0/+5
2021-09-13target/i386: Added VGIF V_IRQ masking capabilityLara Lazier1-0/+12
2021-09-13target/i386: Moved int_ctl into CPUX86State structureLara Lazier3-36/+18
2021-09-13target/i386: Added VGIF featureLara Lazier1-2/+29
2021-09-13target/i386: VMRUN and VMLOAD canonicalizationsLara Lazier1-10/+17
2021-08-13target/i386: Fixed size of constant for WindowsLara Lazier2-2/+2
2021-07-29target/i386: fix typo in ctl_has_irqPaolo Bonzini1-1/+1
2021-07-29target/i386: Added consistency checks for event injectionLara Lazier1-0/+6
2021-07-23i386: do not call cpudef-only models functions for max, host, baseClaudio Fontana1-3/+8
2021-07-23target/i386: Added consistency checks for CR3Lara Lazier2-3/+14
2021-07-22Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...Peter Maydell2-4/+59
2021-07-22target/i386: Added consistency checks for EFERLara Lazier1-0/+39
2021-07-22target/i386: Added consistency checks for CR4Lara Lazier2-3/+9
2021-07-22target/i386: Added V_INTR_PRIO check to virtual interruptsLara Lazier1-1/+11
2021-07-21accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson1-28/+0
2021-07-21target/i386: Implement debug_check_breakpointRichard Henderson1-0/+12
2021-07-21tcg: Rename helper_atomic_*_mmu and provide for user-onlyRichard Henderson1-13/+2
2021-07-13target/i386: Correct implementation for FCS, FIP, FDS and FDPZiqiao Kong2-9/+54
2021-07-13target/i386: Split out do_fninitRichard Henderson1-14/+8
2021-07-13target/i386: Trivial code motion and code style fixZiqiao Kong1-435/+446
2021-07-13target/i386: Tidy hw_breakpoint_removeDmitry Voronetskiy1-2/+2
2021-07-12Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710' into...Peter Maydell2-22/+5
2021-07-09target/i386: Use cpu_breakpoint_test in breakpoint_handlerRichard Henderson1-9/+3
2021-07-09target/i386: Use translator_use_goto_tbRichard Henderson1-12/+2
2021-07-09tcg: Avoid including 'trace-tcg.h' in target translate.cPhilippe Mathieu-Daudé1-1/+0
2021-07-09target/i386: fix exceptions for MOV to DRPaolo Bonzini4-41/+32
2021-07-09target/i386: Added DR6 and DR7 consistency checksLara Lazier1-1/+8
2021-07-09target/i386: Added MSRPM and IOPM size checkLara Lazier1-0/+15
2021-07-06target/i386: Move X86XSaveArea into TCGDavid Edmondson2-0/+58
2021-07-06target/i386: Populate x86_ext_save_areas offsets using cpuid where possibleDavid Edmondson1-0/+20
2021-06-29target/i386: Improve bswap translationRichard Henderson1-10/+4
2021-06-29tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64Richard Henderson1-1/+1
2021-06-16target/i386: Added Intercept CR0 writes checkLara Lazier1-0/+9
2021-06-16target/i386: Added consistency checks for CR0Lara Lazier1-3/+9
2021-06-16target/i386: Added consistency checks for VMRUN intercept and ASIDLara Lazier1-0/+10
2021-06-16target/i386: Refactored intercept checks into cpu_svm_has_interceptLara Lazier1-47/+58
2021-06-04target/i386: Fix decode of cr8Richard Henderson1-0/+1
2021-06-04target/i386: tcg: fix switching from 16-bit to 32-bit tasks or vice versaPaolo Bonzini1-1/+1
2021-06-04target/i386: tcg: fix loading of registers from 16-bit TSSPaolo Bonzini1-14/+11
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