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path: root/target/i386/cpu.h
AgeCommit message (Expand)AuthorFilesLines
2021-09-30i386: Add get/set/migrate support for SGX_LEPUBKEYHASH MSRsSean Christopherson1-0/+1
2021-09-30i386: Add SGX CPUID leaf FEAT_SGX_12_1_EAXSean Christopherson1-0/+1
2021-09-30i386: Add SGX CPUID leaf FEAT_SGX_12_0_EBXSean Christopherson1-0/+1
2021-09-30i386: Add SGX CPUID leaf FEAT_SGX_12_0_EAXSean Christopherson1-0/+1
2021-09-30i386: Add primary SGX CPUID and MSR definesSean Christopherson1-0/+12
2021-09-21include/exec: Move cpu_signal_handler declarationRichard Henderson1-7/+0
2021-09-14user: Remove cpu_get_pic_interrupt() stubsPhilippe Mathieu-Daudé1-1/+1
2021-09-14target/i386: Restrict sysemu-only fpu_helper helpersPhilippe Mathieu-Daudé1-0/+3
2021-09-13target/i386: Added vVMLOAD and vVMSAVE featureLara Lazier1-0/+2
2021-09-13target/i386: Added changed priority check for VIRQLara Lazier1-0/+15
2021-09-13target/i386: Added VGIF V_IRQ masking capabilityLara Lazier1-0/+2
2021-09-13target/i386: Moved int_ctl into CPUX86State structureLara Lazier1-0/+1
2021-09-13target/i386: VMRUN and VMLOAD canonicalizationsLara Lazier1-0/+2
2021-09-13target/i386: add missing bits to CR4_RESERVED_MASKDaniel P. Berrangé1-0/+1
2021-07-22target/i386: Added consistency checks for EFERLara Lazier1-0/+5
2021-07-22target/i386: Added consistency checks for CR4Lara Lazier1-0/+39
2021-07-14Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-misc-20210713' int...Peter Maydell1-0/+2
2021-07-13target/i386: Correct implementation for FCS, FIP, FDS and FDPZiqiao Kong1-0/+2
2021-07-13target/i386: suppress CPUID leaves not defined by the CPU vendorMichael Roth1-0/+3
2021-07-09target/i386: fix exceptions for MOV to DRPaolo Bonzini1-0/+2
2021-07-06target/i386: Move X86XSaveArea into TCGDavid Edmondson1-57/+0
2021-07-06target/i386: Populate x86_ext_save_areas offsets using cpuid where possibleDavid Edmondson1-1/+1
2021-07-06target/i386: Make x86_ext_save_areas visible outside cpu.cDavid Edmondson1-0/+9
2021-07-06target/i386: Pass buffer and length to XSAVE helperDavid Edmondson1-2/+3
2021-07-06target/i386: Clarify the padding requirements of X86XSaveAreaDavid Edmondson1-1/+7
2021-07-06target/i386: Consolidate the X86XSaveArea offset checksDavid Edmondson1-7/+15
2021-07-06target/i386: Declare constants for XSAVE offsetsDavid Edmondson1-7/+23
2021-06-25target/i386: kvm: add support for TSC scalingPaolo Bonzini1-0/+1
2021-06-16target/i386: Added consistency checks for CR0Lara Lazier1-0/+2
2021-06-16target/i386: Refactored intercept checks into cpu_svm_has_interceptLara Lazier1-0/+4
2021-05-31i386: drop FEAT_HYPERV feature leavesVitaly Kuznetsov1-5/+0
2021-05-31i386: stop using env->features[] for filling Hyper-V CPUIDsVitaly Kuznetsov1-0/+1
2021-05-26i386/cpu: Expose AVX_VNNI instruction to guestYang Zhong1-0/+2
2021-05-19target/i386: Inline user cpu_svm_check_intercept_paramRichard Henderson1-0/+8
2021-05-11target/i386: extend pg_mode to more CR0 and CR4 bitsPaolo Bonzini1-0/+8
2021-05-11target/i386: move paging mode constants from SVM to cpu.hPaolo Bonzini1-0/+8
2021-05-10i386: make cpu_load_efer sysemu-onlyClaudio Fontana1-15/+5
2021-05-10i386: separate fpu_helper sysemu-only partsClaudio Fontana1-0/+3
2021-05-10i386: split cpu accelerators from cpu.c, using AccelCPUClassClaudio Fontana1-12/+8
2021-05-02vmstate: Constify some VMStateDescriptionsKeqian Zhu1-1/+1
2021-03-19target/i386: allow modifying TCG phys-addr-bitsPaolo Bonzini1-1/+0
2021-02-25target/i386: Add bus lock debug exception supportChenyi Qiang1-0/+2
2021-02-18i386: Add the support for AMD EPYC 3rd generation processorsBabu Moger1-0/+4
2021-02-16target/i386/hvf: add rdmsr 35H MSR_CORE_THREAD_COUNTVladislav Yaroshchuk1-0/+1
2021-02-08target/i386: Expose VMX entry/exit load pkrs control bitsChenyi Qiang1-0/+2
2021-02-08target/i86: implement PKSPaolo Bonzini1-0/+5
2021-02-08x86/cpu: Populate SVM CPUID feature bitsWei Huang1-10/+14
2021-01-12target/i386: Use X86Seg enum for segment registersPhilippe Mathieu-Daudé1-2/+2
2020-12-16i386: move TCG cpu class initialization to tcg/Claudio Fontana1-86/+0
2020-12-16x86/cpu: Add AVX512_FP16 cpu featureCathy Zhang1-0/+2
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