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2018-11-27vmstate: constify VMStateFieldMarc-André Lureau1-4/+6
Because they are supposed to remain const. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20181114132931.22624-1-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-10-16target/hppa: Raise exception 26 on emulated hardwareHelge Deller1-1/+2
On PCXS chips (PA7000, pa 1.1a), trap #18 is raised on memory faults, while all later chips (>= PA7100) generate either trap #26, #27 or #28 (depending on the fault type). Since the current qemu emulation emulates a B160L machine (with a PA7300LC PCX-L2 chip, we should raise trap #26 (EXCP_DMAR) instead of #18 (EXCP_DMP) on access faults by the Linux kernel to page zero. With the patch we now get the correct output (I tested against real hardware): Kernel Fault: Code=26 (Data memory access rights trap) instead of: Kernel Fault: Code=18 (Data memory protection/unaligned access trap) Signed-off-by: Helge Deller <deller@gmx.de> Message-Id: <20181007205153.GA30270@ls3530.fritz.box> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-06-04Merge remote-tracking branch 'remotes/rth/tags/tcg-next-pull-request' into ↵Peter Maydell1-3/+3
staging tcg-next queue # gpg: Signature made Sat 02 Jun 2018 00:12:42 BST # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/tcg-next-pull-request: tcg: Pass tb and index to tcg_gen_exit_tb separately Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-01tcg: Pass tb and index to tcg_gen_exit_tb separatelyRichard Henderson1-3/+3
Do the cast to uintptr_t within the helper, so that the compiler can type check the pointer argument. We can also do some more sanity checking of the index argument. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-06-01target: Do not include "exec/exec-all.h" if it is not necessaryPhilippe Mathieu-Daudé2-2/+0
Code change produced with: $ git grep '#include "exec/exec-all.h"' | \ cut -d: -f-1 | \ xargs egrep -L "(cpu_address_space_init|cpu_loop_|tlb_|tb_|GETPC|singlestep|TranslationBlock)" | \ xargs sed -i.bak '/#include "exec\/exec-all.h"/d' Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180528232719.4721-10-f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-05-31target/hppa: Include "qemu/log.h" to use qemu_log()Philippe Mathieu-Daudé1-0/+1
Since his inception in 61766fe9e2d, this file uses the qemu_log() API from "qemu/log.h". Include it to allow further includes cleanup. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180528232719.4721-9-f4bug@amsat.org> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-05-17fpu/softfloat: Specialize on snan_bit_is_oneRichard Henderson1-1/+0
Only MIPS requires snan_bit_is_one to be variable. While we are specializing softfloat behaviour, allow other targets to eliminate this runtime check. Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Yongbok Kim <yongbok.kim@mips.com> Cc: David Gibson <david@gibson.dropbear.id.au> Cc: Alexander Graf <agraf@suse.de> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-17target/hppa: Remove floatX_maybe_silence_nan from conversionsRichard Henderson1-2/+0
This is now handled properly by the generic softfloat code. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-09translator: merge max_insns into DisasContextBaseEmilio G. Cota1-5/+2
While at it, use int for both num_insns and max_insns to make sure we have same-type comparisons. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Michael Clark <mjc@sifive.com> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-05-01tcg: Improve TCGv_ptr supportRichard Henderson1-14/+2
Drop TCGV_PTR_TO_NAT and TCGV_NAT_TO_PTR internal macros. Add tcg_temp_local_new_ptr, tcg_gen_brcondi_ptr, tcg_gen_ext_i32_ptr, tcg_gen_trunc_i64_ptr, tcg_gen_extu_ptr_i64, tcg_gen_trunc_ptr_i32. Use inlines instead of macros where possible. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-03-26target/hppa: Include priv level in user-only iaoqRichard Henderson2-10/+6
A recent glibc change relies on the fact that the iaoq must be 3, and computes an address based on that. QEMU had been ignoring the priv level for user-only, which produced an incorrect address. Reported-by: John David Anglin <dave.anglin@bell.net> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-03-19cpu: get rid of unused cpu_init() definesIgor Mammedov1-1/+0
cpu_init(cpu_model) were replaced by cpu_create(cpu_type) so no users are left, remove it. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> (ppc) Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1518000027-274608-6-git-send-email-imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-03-19cpu: add CPU_RESOLVING_TYPE macroIgor Mammedov1-0/+1
it will be used for providing to cpu name resolving class for parsing cpu model for system and user emulation code. Along with change add target to null-machine tests, so that when switch to CPU_RESOLVING_TYPE happens, it would ensure that null-machine usecase still works. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> (m68k) Acked-by: David Gibson <david@gibson.dropbear.id.au> (ppc) Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (tricore) Message-Id: <1518000027-274608-4-git-send-email-imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> [ehabkost: Added macro to riscv too] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-03-12qom: introduce object_class_get_list_sortedPaolo Bonzini1-14/+1
Unify half a dozen copies of very similar code (the only difference being whether comparisons were case-sensitive) and use it also in Tricore, which did not do any sorting of CPU model names. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-02-21target/*/cpu.h: remove softfloat.hAlex Bennée3-2/+2
As cpu.h is another typically widely included file which doesn't need full access to the softfloat API we can remove the includes from here as well. Where they do need types it's typically for float_status and the rounding modes so we move that to softfloat-types.h as well. As a result of not having softfloat in every cpu.h call we now need to add it to various helpers that do need the full softfloat.h definitions. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [For PPC parts] Acked-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-05qdev: use device_class_set_parent_realize/unrealize/reset()Philippe Mathieu-Daudé1-2/+2
changes generated using the following Coccinelle patch: @@ type DeviceParentClass; DeviceParentClass *pc; DeviceClass *dc; identifier parent_fn; identifier child_fn; @@ ( +device_class_set_parent_realize(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->realize; ... -dc->realize = child_fn; | +device_class_set_parent_unrealize(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->unrealize; ... -dc->unrealize = child_fn; | +device_class_set_parent_reset(dc, child_fn, &pc->parent_fn); -pc->parent_fn = dc->reset; ... -dc->reset = child_fn; ) Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180114020412.26160-4-f4bug@amsat.org> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Acked-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-01-31target/hppa: Implement PROBE for system modeRichard Henderson3-17/+40
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Fix 32-bit operand masks for 0E FCVTRichard Henderson1-7/+7
We masked the wrong bits, which prevented some of the 32-bit R registers. E.g. "fcnvxf,sgl,sgl fr22R,fr6R". Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Enable MTTCGRichard Henderson1-0/+6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Implement STWARichard Henderson1-1/+18
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Implement a pause instructionRichard Henderson1-0/+36
This is an extension to the base ISA, but we can use this in the kernel idle loop to reduce the host cpu time consumed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Implement LDSID for system modeHelge Deller1-1/+13
Signed-off-by: Helge Deller <deller@gmx.de> Message-Id: <20180102203145.GA17059@ls3530.fritz.box> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Fix commentHelge Deller1-1/+1
Signed-off-by: Helge Deller <deller@gmx.de> Message-Id: <20171212212319.GA31494@ls3530.fritz.box> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Increase number of temp regsRichard Henderson1-1/+1
HP-UX 10.20 CD contains "add r0, r0, r27" in a delay slot, which uses at least 5 temps. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Only use EXCP_DTLB_MISSRichard Henderson1-1/+3
Unknown why this works, but if we return EXCP_ITLB_MISS we will triple-fault the first userland instruction fetch. Is it something to do with having a combined I/DTLB? Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Implement B,GATE insnRichard Henderson3-0/+57
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Add migration for the cpuRichard Henderson4-0/+184
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Add system registers to gdbstubRichard Henderson1-0/+156
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Optimize for flat addressing spaceRichard Henderson2-10/+30
Linux sets sr4-sr7 all to the same value, which means that we need not do any runtime computation to find out what space to use in forming the GVA. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31target/hppa: Implement halt and reset instructionsHelge Deller3-1/+39
Real hardware would use an external device to control the power. But for the moment let's invent instructions in reserved space, to be used by our custom firmware. Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement SYNCDMA insnRichard Henderson1-1/+2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement LCIRichard Henderson1-0/+20
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement LPARichard Henderson5-5/+58
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement LDWARichard Henderson1-0/+38
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement P*TLB and P*TLBE insnsRichard Henderson3-0/+79
We now have all of the TLB manipulation instructions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement I*TLBA and I*TLBP insnsRichard Henderson3-4/+132
The TLB can now be populated, but it cannot yet be cleared. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Log unimplemented instructionsRichard Henderson1-0/+2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement the interval timerRichard Henderson6-4/+67
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement external interruptsRichard Henderson5-1/+83
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement tlb_fillRichard Henderson3-10/+197
However since HPPA has a software-managed TLB, and the relevant TLB manipulation instructions are not implemented, this does not actually do anything. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement IASQRichard Henderson6-27/+179
Any one TB will have only one space value. If we change spaces, we change TBs. Thus BE and BEV must exit the TB immediately. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Avoid privilege level decrease during branchesRichard Henderson1-5/+47
These instructions force the destination privilege level of the branch destination to be no higher than current. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Use space registers in data operationsRichard Henderson2-147/+201
This changes the system virtual address width to 64-bit and incorporates the space registers into load/store operations. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement unaligned access trapRichard Henderson1-1/+18
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Fill in hppa_cpu_do_interrupt/hppa_cpu_exec_interruptRichard Henderson5-66/+192
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement rfiRichard Henderson4-2/+55
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Adjust insn mask for mfctl,wRichard Henderson1-1/+1
While the E bit is only used for pa2.0 mfctl,w from sar, the otherwise reserved bit does not appear to be decoded. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Add control registersRichard Henderson4-35/+72
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Add space registersRichard Henderson3-11/+77
Not used where they should be yet, but we can copy them. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30target/hppa: Implement the system mask instructionsRichard Henderson3-1/+113
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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