| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2023-11-13 | target/hppa: Reduce TARGET_PHYS_ADDR_SPACE_BITS to 40 | Richard Henderson | 2 | -18/+35 |
| 2023-11-13 | target/hppa: Replace MMU_PHYS_IDX with MMU_ABS_IDX, MMU_ABS_W_IDX | Richard Henderson | 3 | -36/+39 |
| 2023-11-13 | target/hppa: Introduce MMU_IDX_MMU_DISABLED | Richard Henderson | 3 | -11/+14 |
| 2023-11-13 | target/hppa: Fix possible overflow in TLB size calculation | Helge Deller | 1 | -2/+2 |
| 2023-11-13 | target/hppa: Fix calculation of CR_IIASQ back register | Helge Deller | 1 | -1/+1 |
| 2023-11-13 | target/hppa: Use PRIV_P_TO_MMU_IDX in helper_probe | Richard Henderson | 1 | -2/+3 |
| 2023-11-13 | target/hppa: Use only low 2 immediate bits for PROBEI | Richard Henderson | 1 | -1/+1 |
| 2023-11-12 | target/hppa: Mask reserved PSW bits in expand_sm_imm | Helge Deller | 1 | -5/+8 |
| 2023-11-07 | target: Move ArchCPUClass definition to 'cpu.h' | Philippe Mathieu-Daudé | 2 | -16/+14 |
| 2023-11-07 | target: Mention 'cpu-qom.h' is target agnostic | Philippe Mathieu-Daudé | 1 | -1/+1 |
| 2023-11-07 | target: Unify QOM style | Philippe Mathieu-Daudé | 2 | -4/+0 |
| 2023-11-06 | target/hppa: Improve interrupt logging | Richard Henderson | 1 | -8/+4 |
| 2023-11-06 | target/hppa: Update IIAOQ, IIASQ for pa2.0 | Richard Henderson | 2 | -18/+38 |
| 2023-11-06 | target/hppa: Create raise_exception_with_ior | Richard Henderson | 1 | -13/+51 |
| 2023-11-06 | target/hppa: Add unwind_breg to CPUHPPAState | Richard Henderson | 3 | -2/+20 |
| 2023-11-06 | target/hppa: Clear upper bits in mtctl for pa1.x | Helge Deller | 1 | -1/+7 |
| 2023-11-06 | target/hppa: Avoid async_safe_run_on_cpu on uniprocessor system | Richard Henderson | 1 | -1/+7 |
| 2023-11-06 | target/hppa: Add pa2.0 cpu local tlb flushes | Helge Deller | 5 | -12/+84 |
| 2023-11-06 | target/hppa: Implement pa2.0 data prefetch instructions | Richard Henderson | 1 | -1/+9 |
| 2023-11-06 | target/hppa: Return zero for r0 from load_gpr | Richard Henderson | 1 | -3/+1 |
| 2023-11-06 | target/hppa: Precompute zero into DisasContext | Richard Henderson | 1 | -16/+18 |
| 2023-11-06 | target/hppa: Fix interruption based on default PSW | Helge Deller | 2 | -4/+16 |
| 2023-11-06 | target/hppa: Implement PERMH | Richard Henderson | 2 | -0/+31 |
| 2023-11-06 | target/hppa: Implement MIXH, MIXW | Richard Henderson | 2 | -0/+60 |
| 2023-11-06 | target/hppa: Implement HSHLADD, HSHRADD | Richard Henderson | 4 | -2/+76 |
| 2023-11-06 | target/hppa: Implement HSHL, HSHR | Richard Henderson | 2 | -0/+40 |
| 2023-11-06 | target/hppa: Implement HAVG | Richard Henderson | 4 | -0/+22 |
| 2023-11-06 | target/hppa: Implement HSUB | Richard Henderson | 4 | -0/+53 |
| 2023-11-06 | target/hppa: Implement HADD | Richard Henderson | 4 | -1/+79 |
| 2023-11-06 | target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64 | Richard Henderson | 1 | -4/+4 |
| 2023-11-06 | target/hppa: Use tcg_temp_new_i64 not tcg_temp_new | Richard Henderson | 1 | -80/+82 |
| 2023-11-06 | target/hppa: Adjust vmstate_env for pa2.0 tlb | Richard Henderson | 1 | -37/+58 |
| 2023-11-06 | target/hppa: Remove remaining TARGET_REGISTER_BITS redirections | Richard Henderson | 1 | -33/+13 |
| 2023-11-06 | target/hppa: Remove most of the TARGET_REGISTER_BITS redirections | Richard Henderson | 1 | -505/+407 |
| 2023-11-06 | target/hppa: Remove TARGET_REGISTER_BITS | Richard Henderson | 11 | -299/+135 |
| 2023-11-06 | target/hppa: Implement IDTLBT, IITLBT | Richard Henderson | 4 | -13/+100 |
| 2023-11-06 | target/hppa: Implement STDBY | Richard Henderson | 4 | -5/+213 |
| 2023-11-06 | target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM | Richard Henderson | 2 | -0/+8 |
| 2023-11-06 | target/hppa: Implement SHRPD | Richard Henderson | 2 | -32/+73 |
| 2023-11-06 | target/hppa: Implement EXTRD | Richard Henderson | 2 | -13/+36 |
| 2023-11-06 | target/hppa: Implement DEPD, DEPDI | Richard Henderson | 2 | -30/+69 |
| 2023-11-06 | target/hppa: Implement LDD, LDCD, LDDA, STD, STDA | Richard Henderson | 2 | -4/+15 |
| 2023-11-06 | target/hppa: Decode ADDB double-word | Richard Henderson | 1 | -0/+11 |
| 2023-11-06 | target/hppa: Decode CMPIB double-word | Richard Henderson | 2 | -3/+18 |
| 2023-11-06 | target/hppa: Decode d for cmpb instructions | Richard Henderson | 2 | -6/+15 |
| 2023-11-06 | target/hppa: Decode d for bb instructions | Richard Henderson | 2 | -6/+4 |
| 2023-11-06 | target/hppa: Decode d for sub instructions | Richard Henderson | 2 | -17/+17 |
| 2023-11-06 | target/hppa: Decode d for add instructions | Richard Henderson | 2 | -18/+19 |
| 2023-11-06 | target/hppa: Decode d for cmpclr instructions | Richard Henderson | 2 | -8/+9 |
| 2023-11-06 | target/hppa: Decode d for unit instructions | Richard Henderson | 2 | -20/+19 |
