Age | Commit message (Expand) | Author | Files | Lines |
2021-10-15 | target/avr: Drop checks for singlestep_enabled | Richard Henderson | 1 | -15/+4 |
2021-09-21 | include/exec: Move cpu_signal_handler declaration | Richard Henderson | 1 | -2/+0 |
2021-09-16 | Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-6.2-pul... | Peter Maydell | 1 | -5/+3 |
2021-09-16 | target/avr: Fix compiler errors (-Werror=enum-conversion) | Stefan Weil | 1 | -5/+3 |
2021-09-14 | target/avr: Remove pointless use of CONFIG_USER_ONLY definition | Philippe Mathieu-Daudé | 1 | -3/+0 |
2021-07-21 | accel/tcg: Remove TranslatorOps.breakpoint_check | Richard Henderson | 1 | -18/+0 |
2021-07-21 | target/avr: Implement gdb_adjust_breakpoint | Richard Henderson | 4 | -14/+15 |
2021-07-12 | Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710' into... | Peter Maydell | 2 | -7/+10 |
2021-07-09 | target/avr: Mark some helpers noreturn | Richard Henderson | 1 | -4/+4 |
2021-07-09 | target/avr: Use translator_use_goto_tb | Richard Henderson | 1 | -3/+6 |
2021-07-09 | meson: Introduce target-specific Kconfig | Philippe Mathieu-Daudé | 1 | -0/+2 |
2021-06-29 | target/avr: Convert to TranslatorOps | Richard Henderson | 1 | -104/+126 |
2021-06-29 | target/avr: Change ctx to DisasContext* in gen_intermediate_code | Richard Henderson | 1 | -41/+43 |
2021-06-29 | target/avr: Add DisasContextBase to DisasContext | Richard Henderson | 1 | -29/+29 |
2021-05-26 | hw/core: Constify TCGCPUOps | Richard Henderson | 1 | -1/+1 |
2021-05-26 | cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps | Philippe Mathieu-Daudé | 1 | -1/+1 |
2021-05-26 | cpu: Introduce SysemuCPUOps structure | Philippe Mathieu-Daudé | 1 | -0/+6 |
2021-05-26 | cpu: Move AVR target vmsd field from CPUClass to DeviceClass | Philippe Mathieu-Daudé | 2 | -3/+3 |
2021-05-26 | cpu: Rename CPUClass vmsd -> legacy_vmsd | Philippe Mathieu-Daudé | 1 | -1/+1 |
2021-05-13 | target/avr: Ignore unimplemented WDR opcode | Philippe Mathieu-Daudé | 1 | -5/+1 |
2021-03-15 | target/avr: Fix interrupt execution | Ivanov Arkasha | 1 | -1/+3 |
2021-03-15 | target/avr: Fix some comment spelling errors | Lichang Zhao | 1 | -3/+3 |
2021-02-20 | target/avr/cpu: Use device_class_set_parent_realize() | Philippe Mathieu-Daudé | 1 | -3/+1 |
2021-02-05 | cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass | Claudio Fontana | 2 | -7/+17 |
2021-02-05 | cpu: move cc->do_interrupt to tcg_ops | Claudio Fontana | 2 | -3/+3 |
2021-02-05 | cpu: Move tlb_fill to tcg_ops | Eduardo Habkost | 1 | -1/+1 |
2021-02-05 | cpu: Move cpu_exec_* to tcg_ops | Eduardo Habkost | 1 | -1/+1 |
2021-02-05 | cpu: Move synchronize_from_tb() to tcg_ops | Eduardo Habkost | 1 | -1/+1 |
2021-02-05 | cpu: Introduce TCGCpuOperations struct | Eduardo Habkost | 1 | -1/+1 |
2021-01-07 | tcg: Make tb arg to synchronize_from_tb const | Richard Henderson | 1 | -1/+2 |
2020-12-19 | migration: Replace migration's JSON writer by the general one | Markus Armbruster | 1 | -2/+2 |
2020-09-18 | qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros | Eduardo Habkost | 1 | -1/+1 |
2020-09-09 | Use OBJECT_DECLARE_TYPE where possible | Eduardo Habkost | 1 | -4/+2 |
2020-09-09 | Use DECLARE_*CHECKER* macros | Eduardo Habkost | 1 | -6/+2 |
2020-09-09 | Move QOM typedefs and add missing includes | Eduardo Habkost | 1 | -3/+5 |
2020-08-21 | meson: target | Paolo Bonzini | 4 | -36/+22 |
2020-08-21 | meson: rename included C source files to .c.inc | Paolo Bonzini | 3 | -4/+4 |
2020-07-11 | target/avr/disas: Fix store instructions display order | Philippe Mathieu-Daudé | 1 | -10/+10 |
2020-07-11 | target/avr/cpu: Fix $PC displayed address | Philippe Mathieu-Daudé | 1 | -1/+1 |
2020-07-11 | target/avr/cpu: Drop tlb_flush() in avr_cpu_reset() | Philippe Mathieu-Daudé | 1 | -2/+0 |
2020-07-11 | target/avr: Register AVR support with the rest of QEMU | Michael Rolnik | 1 | -0/+34 |
2020-07-11 | target/avr: Add support for disassembling via option '-d in_asm' | Michael Rolnik | 4 | -1/+259 |
2020-07-11 | target/avr: Initialize TCG register variables | Michael Rolnik | 1 | -0/+29 |
2020-07-11 | target/avr: Add instruction translation - CPU main translation function | Michael Rolnik | 1 | -0/+213 |
2020-07-11 | target/avr: Add instruction translation - MCU Control Instructions | Michael Rolnik | 2 | -0/+73 |
2020-07-11 | target/avr: Add instruction translation - Bit and Bit-test Instructions | Michael Rolnik | 2 | -0/+261 |
2020-07-11 | target/avr: Add instruction translation - Data Transfer Instructions | Michael Rolnik | 2 | -0/+1046 |
2020-07-11 | target/avr: Add instruction translation - Branch Instructions | Michael Rolnik | 2 | -0/+576 |
2020-07-11 | target/avr: Add instruction translation - Arithmetic and Logic Instructions | Michael Rolnik | 2 | -0/+896 |
2020-07-11 | target/avr: Add instruction translation - Register definitions | Michael Rolnik | 1 | -0/+142 |