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translate.c
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Author
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2023-10-04
accel/tcg: Replace CPUState.env_ptr with cpu_env()
Richard Henderson
1
-1
/
+1
2023-10-03
tcg: Rename cpu_env to tcg_env
Richard Henderson
1
-32
/
+32
2023-06-05
accel/tcg: Introduce translator_io_start
Richard Henderson
1
-1
/
+0
2023-06-05
tcg: Pass TCGHelperInfo to tcg_gen_callN
Richard Henderson
1
-0
/
+5
2023-05-05
target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_*
Richard Henderson
1
-8
/
+8
2023-03-13
target/avr: Avoid use of tcg_const_i32 throughout
Richard Henderson
1
-15
/
+15
2023-03-13
target/avr: Avoid use of tcg_const_i32 in SBIC, SBIS
Richard Henderson
1
-8
/
+10
2023-03-05
target/avr: Drop tcg_temp_free
Richard Henderson
1
-228
/
+0
2023-03-05
target/avr: Drop R from trans_COM
Richard Henderson
1
-4
/
+0
2023-03-05
target/avr: Drop DisasContext.free_skip_var0
Richard Henderson
1
-19
/
+0
2023-03-01
accel/tcg: Pass max_insn to gen_intermediate_code by pointer
Richard Henderson
1
-1
/
+1
2022-10-26
target/avr: Convert to tcg_ops restore_state_to_opc
Richard Henderson
1
-6
/
+0
2022-09-06
accel/tcg: Add pc and host_pc params to gen_intermediate_code
Richard Henderson
1
-2
/
+3
2022-09-01
target/avr: Disable interrupts when env->skip set
Richard Henderson
1
-4
/
+22
2022-04-20
exec/translator: Pass the locked filepointer to disas_log hook
Richard Henderson
1
-3
/
+4
2021-10-15
target/avr: Drop checks for singlestep_enabled
Richard Henderson
1
-15
/
+4
2021-09-16
target/avr: Fix compiler errors (-Werror=enum-conversion)
Stefan Weil
1
-5
/
+3
2021-07-21
accel/tcg: Remove TranslatorOps.breakpoint_check
Richard Henderson
1
-18
/
+0
2021-07-21
target/avr: Implement gdb_adjust_breakpoint
Richard Henderson
1
-14
/
+0
2021-07-09
target/avr: Use translator_use_goto_tb
Richard Henderson
1
-3
/
+6
2021-06-29
target/avr: Convert to TranslatorOps
Richard Henderson
1
-104
/
+126
2021-06-29
target/avr: Change ctx to DisasContext* in gen_intermediate_code
Richard Henderson
1
-41
/
+43
2021-06-29
target/avr: Add DisasContextBase to DisasContext
Richard Henderson
1
-29
/
+29
2020-08-21
meson: target
Paolo Bonzini
1
-1
/
+1
2020-08-21
meson: rename included C source files to .c.inc
Paolo Bonzini
1
-1
/
+1
2020-07-11
target/avr: Add support for disassembling via option '-d in_asm'
Michael Rolnik
1
-0
/
+12
2020-07-11
target/avr: Initialize TCG register variables
Michael Rolnik
1
-0
/
+29
2020-07-11
target/avr: Add instruction translation - CPU main translation function
Michael Rolnik
1
-0
/
+213
2020-07-11
target/avr: Add instruction translation - MCU Control Instructions
Michael Rolnik
1
-0
/
+65
2020-07-11
target/avr: Add instruction translation - Bit and Bit-test Instructions
Michael Rolnik
1
-0
/
+247
2020-07-11
target/avr: Add instruction translation - Data Transfer Instructions
Michael Rolnik
1
-0
/
+990
2020-07-11
target/avr: Add instruction translation - Branch Instructions
Michael Rolnik
1
-0
/
+543
2020-07-11
target/avr: Add instruction translation - Arithmetic and Logic Instructions
Michael Rolnik
1
-0
/
+820
2020-07-11
target/avr: Add instruction translation - Register definitions
Michael Rolnik
1
-0
/
+142