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2025-05-14target/arm/ptw: compile file once (system)Pierrick Bouvier1-1/+1
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250512180502.2395029-32-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/ptw: replace TARGET_AARCH64 by CONFIG_ATOMIC64 from arm_casq_ptwPierrick Bouvier1-1/+1
This function needs 64 bit compare exchange, so we hide implementation for hosts not supporting it (some 32 bit target, which don't run 64 bit guests anyway). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250512180502.2395029-31-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/ptw: replace target_ulong with int64_tPierrick Bouvier1-2/+2
sextract64 returns a signed value. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250512180502.2395029-30-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/cortex-regs: compile file once (system)Pierrick Bouvier1-1/+1
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250512180502.2395029-29-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/arm-powerctl: compile file once (system)Pierrick Bouvier1-1/+1
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250512180502.2395029-28-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/arch_dump: compile file once (system)Pierrick Bouvier1-1/+1
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250512180502.2395029-27-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/arch_dump: remove TARGET_AARCH64 conditionalsPierrick Bouvier1-6/+0
Associated code is protected by cpu_isar_feature(aa64*) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250512180502.2395029-26-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/vfp_fpscr: compile file twice (user, system)Pierrick Bouvier1-1/+2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250512180502.2395029-25-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/helper: compile file twice (user, system)Pierrick Bouvier1-1/+2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250512180502.2395029-24-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/helper: remove remaining TARGET_AARCH64Pierrick Bouvier1-8/+1
They were hiding aarch64_sve_narrow_vq and aarch64_sve_change_el, which we can expose safely. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250512180502.2395029-23-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/helper: expose aarch64 cpu registrationPierrick Bouvier1-7/+0
associated define_arm_cp_regs are guarded by "cpu_isar_feature(aa64_*)", so it's safe to expose that code for arm target (32 bit). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250512180502.2395029-22-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/helper: replace target_ulong by vaddrPierrick Bouvier1-1/+1
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250512180502.2395029-21-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/helper: restrict include to common helpersPierrick Bouvier1-1/+3
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250512180502.2395029-20-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/debug_helper: compile file twice (user, system)Pierrick Bouvier1-2/+8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250512180502.2395029-19-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/debug_helper: remove target_ulongPierrick Bouvier1-1/+1
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250512180502.2395029-18-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/debug_helper: only include common helpersPierrick Bouvier1-1/+3
Avoid pulling helper.h which contains TARGET_AARCH64. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250512180502.2395029-17-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/helper: extract common helpersPierrick Bouvier2-1150/+1155
Allow later commits to include only the "new" tcg/helper.h, thus preventing to pull aarch64 helpers (+ target/arm/helper.h contains a ifdef TARGET_AARCH64). Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250512180502.2395029-16-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/helper: use vaddr instead of target_ulong for probe_accessPierrick Bouvier2-2/+2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250512180502.2395029-15-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/helper: use vaddr instead of target_ulong for exception_pc_alignmentPierrick Bouvier4-4/+4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250512180502.2395029-14-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/cpu32-stubs.c: compile file twice (user, system)Pierrick Bouvier1-7/+7
It could be squashed with commit introducing it, but I would prefer to introduce target/arm/cpu.c first. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250512180502.2395029-12-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/cpu: compile file twice (user, system) onlyPierrick Bouvier1-1/+7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250512180502.2395029-11-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/cpu: remove TARGET_AARCH64 in arm_cpu_finalize_featuresPierrick Bouvier3-6/+33
Need to stub cpu64 finalize functions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250512180502.2395029-10-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/cpu: remove TARGET_AARCH64 around aarch64_cpu_dump_state commonPierrick Bouvier1-11/+0
Call is guarded by is_a64(env), so it's safe to expose without needing to assert anything. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250512180502.2395029-9-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/cpu: remove TARGET_BIG_ENDIAN dependencyPierrick Bouvier1-1/+2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250512180502.2395029-8-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/cpu: move arm_cpu_kvm_set_irq to kvm.cPierrick Bouvier4-31/+36
Allow to get rid of CONFIG_KVM in target/arm/cpu.c Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250512180502.2395029-7-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm/kvm-stub: add kvm_arm_reset_vcpu stubPierrick Bouvier1-0/+5
Needed in target/arm/cpu.c once kvm is possible. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250512180502.2395029-6-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm: move kvm stubs and remove CONFIG_KVM from kvm_arm.hPierrick Bouvier2-82/+78
Add a forward decl for struct kvm_vcpu_init to avoid pulling all kvm headers. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250512180502.2395029-5-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm: Replace target_ulong -> vaddr for HWBreakpointPhilippe Mathieu-Daudé2-6/+6
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250512180502.2395029-2-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-14target/arm: Remove TYPE_AARCH64_CPUPeter Maydell5-59/+2
The TYPE_AARCH64_CPU class is an abstract type that is the parent of all the AArch64 CPUs. It now has no special behaviour of its own, so we can eliminate it and make the AArch64 CPUs directly inherit from TYPE_ARM_CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250429132200.605611-8-peter.maydell@linaro.org
2025-05-14target/arm/kvm: don't check TYPE_AARCH64_CPUPeter Maydell1-2/+1
We want to merge TYPE_AARCH64_CPU with TYPE_ARM_CPU, so enforcing in kvm_arch_init_vcpu() that the CPU class is a subclass of TYPE_AARCH64_CPU will no longer be possible. It's safe to just remove this test, because any purely-AArch32 CPU will fail the "kvm_target isn't set" check, because we no longer support the old AArch32-host KVM setup and so CPUs like the Cortex-A7 no longer set cpu->kvm_target. Only the 'host', 'max', and the odd special cases 'cortex-a53' and 'cortex-a57' set kvm_target. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250429132200.605611-7-peter.maydell@linaro.org
2025-05-14target/arm: Move aarch64 CPU property code to TYPE_ARM_CPUPeter Maydell2-33/+36
The only thing we have left in the TYPE_AARCH64_CPU class that makes it different to TYPE_ARM_CPU is that we register the handling of the "aarch64" property there. Move the handling of this property to the base class, where we make it a property of the object rather than of the class, and add it to the CPU if it has the ARM_FEATURE_AARCH64 property present at init. This is in line with how we handle other Arm CPU properties, and should not change which CPUs it's visible for. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250429132200.605611-6-peter.maydell@linaro.org
2025-05-14target/arm: Present AArch64 gdbstub based on ARM_FEATURE_AARCH64Peter Maydell1-1/+1
Currently we provide an AArch64 gdbstub for CPUs which are TYPE_AARCH64_CPU, and an AArch32 gdbstub for those which are only TYPE_ARM_CPU. This mostly does the right thing, except in the corner case of KVM with -cpu host,aarch64=off. That produces a CPU which is TYPE_AARCH64_CPU but which has ARM_FEATURE_AARCH64 removed and which to the guest is in AArch32 mode. Now we have moved all the handling of AArch64-vs-AArch32 gdbstub behaviour into TYPE_ARM_CPU we can change the condition we use for whether to select the AArch64 gdbstub to look at ARM_FEATURE_AARCH64. This will mean that we now correctly provide an AArch32 gdbstub for aarch64=off CPUs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250429132200.605611-5-peter.maydell@linaro.org
2025-05-07Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi1-2/+2
* ci: enable RISC-V cross jobs * rust: bump minimum supported version to 1.77 * rust: enable uninlined_format_args lint * initial Emscripten support * small fixes # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCgAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmgaFq8UHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroOxAAf/YPKw5KAoE5SwUqJ0oSOMHrU0w4jc # A2Qiw1uziA6kDmUMUXwWR7Qbd8V7jtihGrgTrIPopeavgWWQeNsBHjN4WxHRI7aq # +429rjzFo9V9tSfgp6UcLQSk/9kC4ygEwPnesHpKd27fS6z9Wg4AQkj1iFipR179 # wC3fqwOqqWZSjfUd7wjo7McFYZgL5j/cxmFXePh8+fdT+6PUKdG9nRW86KUPDZ+A # 8HxcuOW7GZd+LhnYUhi7vlLFo/RgVsGQWj0Q4BDJvUkKa13t9UUCGff7uQP2AC3v # ny0gWDcmbWY1L/QXyNzhgd44X4LAjCmpnonlYnrdZizEmhv3aByd+fANgw== # =uIJK # -----END PGP SIGNATURE----- # gpg: Signature made Tue 06 May 2025 10:03:27 EDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (30 commits) gitlab: Enable CI for wasm build tests: Add Dockerfile containing dependencies for Emscripten build meson: Add wasm build in build scripts util: Add coroutine backend for emscripten util: exclude mmap-alloc.c from compilation target on Emscripten Disable options unsupported on Emscripten include/qemu/osdep.h: Add Emscripten-specific OS dependencies block: Fix type conflict of the copy_file_range stub block: Add including of ioctl header for Emscripten build util/cacheflush.c: Update cache flushing mechanism for Emscripten include/glib-compat.h: Poison g_list_sort and g_slist_sort target/s390x: Fix type conflict of GLib function pointers target/ppc: Fix type conflict of GLib function pointers target/i386/cpu.c: Fix type conflict of GLib function pointers target/arm/helper.c: Fix type conflict of GLib function pointers docs: build-system: fix typo ci: run RISC-V cross jobs by default rust: clippy: enable uninlined_format_args lint target/i386/emulate: fix target_ulong format strings docs: rust: update for newer minimum supported version ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-07Merge tag 'pull-target-arm-20250506' of ↵Stefan Hajnoczi6-87/+70
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * hw/arm/npcm8xx_boards: Correct valid_cpu_types setting of NPCM8XX SoC * arm/hvf: fix crashes when using gdbstub * target/arm/ptw: fix arm_cpu_get_phys_page_attrs_debug * hw/arm/virt: Remove deprecated old versions of 'virt' machine * tests/functional: Add test for imx8mp-evk board with USDHC coverage * hw/arm: Attach PSPI module to NPCM8XX SoC * target/arm: Don't assert() for ISB/SB inside IT block * docs: Don't define duplicate label in qemu-block-drivers.rst.inc * target/arm/kvm: Drop support for kernels without KVM_ARM_PREFERRED_TARGET * hw/pci-host/designware: Fix viewport configuration * hw/gpio/imx_gpio: Fix interpretation of GDIR polarity # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmgaH50ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3l4ED/0QOV6oev1ILqA1INBjY7Ct # VrjzjsynFnUkyU0MLKyuK+mBRYmeR1OWtIRTkbgIsRA23XqV4de/BhGsVCGrRA0r # VS/hV2kTQM0GYU2dCr9LpOC3jX0dDzft5uW9GjW/sW9infAwXRwKhGgkIV6q/G5V # Y6cMN7UXrOnomF8Spk5VvK8HH9OHV/fuSlWenk9X1bXPpVQ3jymqZ1eRSDXOzDdM # uP6lVdI3oHCpRPeXKa1EA8cfQa9M/y9XSzDIrF8OTZKVcIzbX8/XR+y74e4UMIvK # DD3nAuAXcezy3286Pu7OfciRBJfq3eFHZVXOKfQWFI3MStPmexKqoHm8JtQxXJOT # uJdaugItLahlPtNk41nAydYzYimK/MBKCWAfTqecEhZ9Cd64jeOPM9zXwRkXwyuu # n9XQUhm5Ll22urd4q2M8cCxKBP2OoaEBFS4Hn9uDpVDcWpRMLe2DP7ywzZjdLU9b # jLSlana5+wpMuwIasXlNzWgT37RA+xlDE2Snaz7K/Z3JV/XNZAZD6WXV72zTzhFs # EI10edHI+JXXlbT1Ev/yVv4cN9h/Kr3hyoOKat2ySaomW26H27wNPuvPTto4rCYU # 6VQJmJvwPSBWELI5eRbcN269K0ar1UXUsvDsy97cq35me3gFvfAZFksLpnPWKef6 # pvwwPuxLWQXs+chepuQyXA== # =c21p # -----END PGP SIGNATURE----- # gpg: Signature made Tue 06 May 2025 10:41:33 EDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20250506' of https://git.linaro.org/people/pmaydell/qemu-arm: (32 commits) hw/arm/virt: Remove deprecated virt-4.0 machine hw/arm/virt: Remove deprecated virt-3.1 machine hw/arm/virt: Remove deprecated virt-3.0 machine hw/arm/virt: Update comment about Multiprocessor Affinity Register hw/gpio/imx_gpio: Fix interpretation of GDIR polarity hw/pci-host/designware: Fix viewport configuration hw/pci-host/designware: Remove unused include target/arm/kvm: Drop support for kernels without KVM_ARM_PREFERRED_TARGET docs: Don't define duplicate label in qemu-block-drivers.rst.inc target/arm: Don't assert() for ISB/SB inside IT block hw/arm: Attach PSPI module to NPCM8XX SoC tests/functional: Add test for imx8mp-evk board with USDHC coverage hw/arm/virt: Remove VirtMachineClass::no_highmem_ecam field hw/arm/virt: Remove deprecated virt-2.12 machine hw/arm/virt: Remove VirtMachineClass::smbios_old_sys_ver field hw/arm/virt: Remove deprecated virt-2.11 machine hw/arm/virt: Remove deprecated virt-2.10 machine hw/arm/virt: Remove deprecated virt-2.9 machine hw/arm/virt: Remove VirtMachineClass::claim_edge_triggered_timers field hw/arm/virt: Remove deprecated virt-2.8 machine ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-06target/arm/kvm: Drop support for kernels without KVM_ARM_PREFERRED_TARGETPeter Maydell3-53/+9
Our KVM code includes backwards compatibility support for ancient kernels which don't support the KVM_ARM_PREFERRED_TARGET ioctl. This ioctl was introduced in kernel commit 42c4e0c77ac91 in September 2013 and is in v3.12, so it's reasonable to assume it's present. (We already dropped support for kernels without KVM_CAP_DEVICE_CTRL, a feature added to the kernel in April 2013, in our commit 84f298ea3e; so there are only about six months' worth of kernels, from v3.9 to v3.11, that we don't already fail to run on and that this commit is dropping handling for.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250318114222.1018200-1-peter.maydell@linaro.org
2025-05-06target/arm: Don't assert() for ISB/SB inside IT blockPeter Maydell1-1/+2
If the guest code has an ISB or SB insn inside an IT block, we generate incorrect code which trips a TCG assertion: qemu-system-arm: ../tcg/tcg-op.c:3343: void tcg_gen_goto_tb(unsigned int): Assertion `(tcg_ctx->goto_tb_issue_mask & (1 << idx)) == 0' failed. This is because we call gen_goto_tb(dc, 1, ...) twice: brcond_i32 ZF,$0x0,ne,$L1 add_i32 pc,pc,$0x4 goto_tb $0x1 exit_tb $0x73d948001b81 set_label $L1 add_i32 pc,pc,$0x4 goto_tb $0x1 exit_tb $0x73d948001b81 Both calls are in arm_tr_tb_stop(), one for the DISAS_NEXT/DISAS_TOO_MANY handling, and one for the dc->condjump condition-failed codepath. The DISAS_NEXT handling doesn't have this problem because arm_post_translate_insn() does the handling of "emit the label for the condition-failed conditional execution" and so arm_tr_tb_stop() doesn't have dc->condjump set. But for DISAS_TOO_MANY we don't do that. Fix the bug by making arm_post_translate_insn() handle the DISAS_TOO_MANY case. This only affects the SB and ISB insns when used in Thumb mode inside an IT block: only these insns specifically set is_jmp to TOO_MANY, and their A32 encodings are unconditional. For the major TOO_MANY case (breaking the TB because it would cross a page boundary) we do that check and set is_jmp to TOO_MANY only after the call to arm_post_translate_insn(); so arm_post_translate_insn() sees is_jmp == DISAS_NEXT, and we emit the correct code for that situation. With this fix we generate the somewhat more sensible set of TCG ops: brcond_i32 ZF,$0x0,ne,$L1 set_label $L1 add_i32 pc,pc,$0x4 goto_tb $0x1 exit_tb $0x7c5434001b81 (NB: the TCG optimizer doesn't optimize out the jump-to-next, but we can't really avoid emitting it because we don't know at the point we're emitting the handling for the condexec check whether this insn is going to happen to be a nop for us or not.) Cc: qemu-stable@nongnu.org Fixes: https://gitlab.com/qemu-project/qemu/-/issues/2942 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250501125544.727038-1-peter.maydell@linaro.org
2025-05-06target/arm/helper.c: Fix type conflict of GLib function pointersKohei Tokunaga1-2/+2
On Emscripten, function pointer casts can result in runtime failures due to strict function signature checks. This affects the use of g_list_sort and g_slist_sort, which internally perform function pointer casts that are not supported by Emscripten. To avoid these issues, g_list_sort_with_data and g_slist_sort_with_data should be used instead, as they do not rely on function pointer casting. Signed-off-by: Kohei Tokunaga <ktokunaga.mail@gmail.com> Link: https://lore.kernel.org/r/7d56c82382e8b4f1694b6d7883b2ce3084fdc72d.1745820062.git.ktokunaga.mail@gmail.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-06target/arm/ptw: fix arm_cpu_get_phys_page_attrs_debugPierrick Bouvier1-1/+21
It was reported that QEMU monitor command gva2gpa was reporting unmapped memory for a valid access (qemu-system-aarch64), during a copy from kernel to user space (__arch_copy_to_user symbol in Linux) [1]. This was affecting cpu_memory_rw_debug also, which is used in numerous places in our codebase. After investigating, the problem was specific to arm_cpu_get_phys_page_attrs_debug. When performing user access from a privileged space, we need to do a second lookup for user mmu idx, following what get_a64_user_mem_index is doing at translation time. [1] https://lists.nongnu.org/archive/html/qemu-discuss/2025-04/msg00013.html Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250414153027.1486719-5-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06target/arm/ptw: extract arm_cpu_get_phys_pagePierrick Bouvier1-10/+14
Allow to call that function easily several times in next commit. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250414153027.1486719-4-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06target/arm/ptw: get current security_space for current mmu_idxPierrick Bouvier1-1/+1
It should be equivalent to previous code. Allow to call common function to get a page address later. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250414153027.1486719-3-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06target/arm/ptw: extract arm_mmu_idx_to_security_spacePierrick Bouvier1-7/+14
We'll reuse this function later. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20250414153027.1486719-2-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-06hvf: avoid repeatedly setting trap debug for each cpuMads Ynddal1-16/+11
hvf_arch_set_traps is already called from a context of a specific CPUState, so we don't need to do a nested CPU_FOREACH. It also results in an error from hv_vcpu_set_sys_reg, as it may only be called from the thread owning the vCPU. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2895 Tested-by: Daniel Gomez <da.gomez@samsung.com> Signed-off-by: Mads Ynddal <m.ynddal@samsung.com> Reported-by: Daniel Gomez <da.gomez@samsung.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20250402135229.28143-2-mads@ynddal.dk Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-05-05accel/tcg: Remove TARGET_PAGE_DATA_SIZERichard Henderson2-6/+2
This macro is used by only one target, and even then under unusual conditions -- AArch64 with mmap's PROT_MTE flag. Since page size for aarch64-linux-user is variable, the per-page data size is also variable. Since page_reset_target_data via target_munmap does not have ready access to CPUState, simply pass in the size from the first allocation and remember that. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-05accel/tcg: Move TARGET_TAGGED_ADDRESSES to TCGCPUOps.untagged_addrRichard Henderson3-38/+28
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30accel/tcg: Split out accel/tcg/helper-retaddr.hRichard Henderson3-0/+3
Move set_helper_retaddr and clear_helper_retaddr to a new header file. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOpsRichard Henderson4-1/+5
Move the global function name to a hook on TCGCPUOps. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30accel/tcg: Return TCGTBCPUState from cpu_get_tb_cpu_stateRichard Henderson1-6/+11
Combine 3 different pointer returns into one structure return. Include a cflags field in TCGTBCPUState, not filled in by cpu_get_tb_cpu_state, but used by all callers. This fills a hole in the structure and is useful in some subroutines. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30target/arm: Unexport assert_hflags_rebuild_correctlyRichard Henderson3-7/+1
This function is no longer used outside of hflags.c. We can remove the stub as well. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30target/arm: Move cpu_get_tb_cpu_state to hflags.cRichard Henderson2-110/+110
This is a tcg-specific function, so move it to a tcg file. Also move mve_no_pred, a static function only used within cpu_get_tb_cpu_state. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30accel/tcg: Hoist cpu_get_tb_cpu_state decl to accl/tcg/cpu-ops.hRichard Henderson2-3/+1
For some targets, simply remove the local definition. For other targets, move the inline definition out of line. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2025-09-19 06:06:28 +0000