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2021-03-08target/arm: Restrict v7A TCG cpus to TCG accelPhilippe Mathieu-Daudé2-335/+318
2021-03-05target/arm/cpu: Update coding style to make checkpatch.pl happyPhilippe Mathieu-Daudé1-4/+8
2021-03-05target/arm: Restrict v8M IDAU to TCGPhilippe Mathieu-Daudé2-7/+8
2021-03-05target/arm: Use TCF0 and TFSRE0 for unprivileged tag checksPeter Collingbourne2-5/+10
2021-03-05target/arm: Speed up aarch64 TBL/TBXRichard Henderson4-84/+56
2021-03-05target/arm: Set ID_PFR2.SSBS to 1 for "max" 32-bit CPURebecca Cran1-0/+4
2021-03-05target/arm: Enable FEAT_SSBS for "max" AARCH64 CPURebecca Cran1-0/+5
2021-03-05target/arm: Add support for FEAT_SSBS, Speculative Store Bypass SafeRebecca Cran4-1/+69
2021-02-18exec: Move TranslationBlock typedef to qemu/typedefs.hRichard Henderson1-2/+1
2021-02-17Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into ...Peter Maydell1-0/+5
2021-02-16sev/i386: Don't allow a system reset under an SEV-ES guestTom Lendacky1-0/+5
2021-02-16target/arm: Enable MTE for user-onlyRichard Henderson1-0/+15
2021-02-16target/arm: Add allocation tag storage for user modeRichard Henderson1-2/+27
2021-02-16linux-user/aarch64: Signal SEGV_MTEAERR for async tag check errorRichard Henderson1-0/+10
2021-02-16linux-user/aarch64: Pass syndrome to EXC_*_ABORTRichard Henderson1-6/+9
2021-02-16target/arm: Split out syndrome.h from internals.hRichard Henderson2-244/+274
2021-02-16linux-user/aarch64: Implement PROT_MTERichard Henderson1-0/+1
2021-02-16target/arm: Use the proper TBI settings for linux-userRichard Henderson2-9/+5
2021-02-16target/arm: Improve gen_top_byte_ignoreRichard Henderson1-11/+14
2021-02-16linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLERichard Henderson2-0/+34
2021-02-16exec: Use cpu_untagged_addr in g2h; split out g2h_untaggedRichard Henderson1-2/+2
2021-02-11target/arm: Correctly initialize MDCR_EL2.HPMNDaniel Müller1-5/+4
2021-02-11target/arm: Set ID_PFR0.DIT to 1 for "max" 32-bit CPURebecca Cran1-0/+4
2021-02-11target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPURebecca Cran1-0/+5
2021-02-11target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstateRebecca Cran3-18/+42
2021-02-11target/arm: Add support for FEAT_DIT, Data Independent TimingRebecca Cran4-0/+52
2021-02-11target/arm: Fix SCR RES1 handlingMike Nawrocki2-2/+19
2021-02-11target/arm: Don't migrate CPUARMState.featuresAaron Lindsay1-1/+1
2021-02-05cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana4-24/+58
2021-02-05cpu: move debug_check_watchpoint to tcg_opsClaudio Fontana1-2/+2
2021-02-05cpu: move adjust_watchpoint_address to tcg_opsClaudio Fontana1-1/+1
2021-02-05cpu: move do_unaligned_access to tcg_opsClaudio Fontana1-1/+1
2021-02-05cpu: move cc->transaction_failed to tcg_opsClaudio Fontana1-2/+2
2021-02-05cpu: move cc->do_interrupt to tcg_opsClaudio Fontana2-7/+6
2021-02-05target/arm: do not use cc->do_interrupt for KVM directlyClaudio Fontana2-4/+6
2021-02-05cpu: Move debug_excp_handler to tcg_opsEduardo Habkost1-1/+1
2021-02-05cpu: Move tlb_fill to tcg_opsEduardo Habkost1-1/+1
2021-02-05cpu: Move cpu_exec_* to tcg_opsEduardo Habkost3-3/+11
2021-02-05cpu: Move synchronize_from_tb() to tcg_opsEduardo Habkost1-1/+3
2021-02-05cpu: Introduce TCGCpuOperations structEduardo Habkost1-1/+1
2021-01-29target/arm: Replace magic value by MMU_DATA_LOAD definitionPhilippe Mathieu-Daudé1-1/+1
2021-01-29target/arm: Conditionalize DBGDIDRRichard Henderson1-6/+15
2021-01-29target/arm: Implement ID_PFR2Richard Henderson3-2/+5
2021-01-19target/arm/m_helper: Silence GCC 10 maybe-uninitialized errorPhilippe Mathieu-Daudé1-1/+1
2021-01-19target/arm: Update REV, PUNPK for pred_descRichard Henderson2-13/+8
2021-01-19target/arm: Update ZIP, UZP, TRN for pred_descRichard Henderson2-17/+13
2021-01-19target/arm: Update PFIRST, PNEXT for pred_descRichard Henderson2-6/+7
2021-01-19target/arm: Introduce PREDDESC field definitionsRichard Henderson1-0/+9
2021-01-19target/arm: refactor vae1_tlbmask()Rémi Denis-Courmont1-14/+11
2021-01-19target/arm: enable Secure EL2 in max CPURémi Denis-Courmont1-0/+1