riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-06-21	target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access	Peter Maydell	1	-30/+72
2021-06-21	target/arm: Don't NOCP fault for FPCXT_NS accesses	Peter Maydell	5	-528/+542
2021-06-21	target/arm: Handle FPU being disabled in FPCXT_NS accesses	Peter Maydell	1	-2/+30
2021-06-21	target/arm/translate-vfp.c: Whitespace fixes	Peter Maydell	1	-6/+5
2021-06-21	target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors	Peter Maydell	1	-5/+1
2021-06-16	bitops.h: Provide hswap32(), hswap64(), wswap64() swapping operations	Peter Maydell	1	-20/+0
2021-06-16	target/arm: Move expand_pred_b() data to vec_helper.c	Peter Maydell	3	-99/+109
2021-06-16	target/arm: Add framework for MVE decode	Peter Maydell	5	-0/+53
2021-06-16	target/arm: Implement MVE LETP insn	Peter Maydell	2	-9/+97
2021-06-16	target/arm: Implement MVE DLSTP	Peter Maydell	2	-5/+27
2021-06-16	target/arm: Implement MVE WLSTP insn	Peter Maydell	2	-3/+42
2021-06-16	target/arm: Implement MVE LCTP	Peter Maydell	2	-0/+26
2021-06-16	target/arm: Let vfp_access_check() handle late NOCP checks	Peter Maydell	1	-5/+15
2021-06-16	target/arm: Add handling for PSR.ECI/ICI	Peter Maydell	5	-5/+133
2021-06-16	target/arm: Handle VPR semantics in existing code	Peter Maydell	3	-11/+57
2021-06-16	target/arm: Enable FPSCR.QC bit for MVE	Peter Maydell	2	-10/+23
2021-06-16	target/arm: Provide and use H8 and H1_8 macros	Peter Maydell	3	-137/+143
2021-06-16	target/arm: Fix mte page crossing test	Richard Henderson	1	-1/+1
2021-06-15	target/arm: Diagnose UNALLOCATED in disas_simd_three_reg_same_fp16	Richard Henderson	1	-30/+48
2021-06-15	target/arm: Remove fprintf from disas_simd_mod_imm	Richard Henderson	1	-1/+0
2021-06-15	target/arm: Diagnose UNALLOCATED in disas_simd_two_reg_misc_fp16	Richard Henderson	1	-2/+2
2021-06-03	target/arm: Enable BFloat16 extensions	Richard Henderson	3	-0/+7
2021-06-03	target/arm: Implement bfloat widening fma (indexed)	Richard Henderson	7	-1/+82
2021-06-03	target/arm: Implement bfloat widening fma (vector)	Richard Henderson	7	-4/+73
2021-06-03	target/arm: Implement bfloat16 matrix multiply accumulate	Richard Henderson	7	-3/+81
2021-06-03	target/arm: Implement bfloat16 dot product (indexed)	Richard Henderson	7	-9/+80
2021-06-03	target/arm: Implement bfloat16 dot product (vector)	Richard Henderson	7	-0/+89
2021-06-03	target/arm: Implement vector float32 to bfloat16 conversion	Richard Henderson	9	-0/+95
2021-06-03	target/arm: Implement scalar float32 to bfloat16 conversion	Richard Henderson	5	-0/+51
2021-06-03	target/arm: Unify unallocated path in disas_fp_1src	Richard Henderson	1	-9/+6
2021-06-03	target/arm: Add isar_feature_{aa32, aa64, aa64_sve}_bf16	Richard Henderson	1	-0/+15
2021-06-03	target/arm: use raise_exception_ra for stack limit exception	Jamie Iles	2	-10/+4
2021-06-03	target/arm: use raise_exception_ra for MTE check failure	Jamie Iles	1	-9/+3
2021-06-03	target/arm: fold do_raise_exception into raise_exception	Jamie Iles	1	-10/+2
2021-06-03	target/arm: fix missing exception class	Jamie Iles	1	-2/+9
2021-06-03	target/arm: Mark LDS{MIN,MAX} as signed operations	Richard Henderson	1	-3/+10
2021-06-03	target/arm: Allow board models to specify initial NS VTOR	Peter Maydell	2	-0/+12
2021-06-03	target/arm: Make FPSCR.LTPSIZE writable for MVE	Peter Maydell	3	-4/+9
2021-06-03	target/arm: Implement M-profile VPR register	Peter Maydell	3	-0/+63
2021-06-03	target/arm: Fix return values in fp_sysreg_checks()	Peter Maydell	1	-3/+3
2021-06-03	target/arm: Add MVE check to VMOV_reg_sp and VMOV_reg_dp	Peter Maydell	1	-2/+13
2021-06-03	target/arm: Move fpsp/fpdp isar check into callers of do_vfp_2op_sp/dp	Peter Maydell	1	-18/+19
2021-06-03	target/arm: Update feature checks for insns which are "MVE or FP"	Peter Maydell	1	-19/+29
2021-06-03	target/arm: Add isar feature check functions for MVE	Peter Maydell	1	-0/+22
2021-06-02	docs: fix references to docs/devel/tracing.rst	Stefano Garzarella	1	-1/+1
2021-05-26	hw/core: Constify TCGCPUOps	Richard Henderson	2	-2/+2
2021-05-26	cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps	Philippe Mathieu-Daudé	1	-1/+1
2021-05-26	cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps	Philippe Mathieu-Daudé	1	-1/+1
2021-05-26	cpu: Move CPUClass::write_elf* to SysemuCPUOps	Philippe Mathieu-Daudé	1	-2/+2
2021-05-26	cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps	Philippe Mathieu-Daudé	1	-1/+1