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2018-03-01arm/translate-a64: add all FP16 ops in simd_scalar_pairwiseAlex Bennée1-26/+54
2018-03-01arm/translate-a64: add FP16 FMOV to simd_mod_immAlex Bennée1-10/+25
2018-03-01arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16Alex Bennée1-0/+7
2018-03-01arm/helper.c: re-factor rsqrte and add rsqrte_f16Alex Bennée2-118/+104
2018-03-01arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16Alex Bennée3-0/+19
2018-03-01arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16Alex Bennée3-0/+34
2018-03-01arm/translate-a64: add FP16 FRECPEAlex Bennée1-0/+8
2018-03-01arm/helper.c: re-factor recpe and add recepe_f16Alex Bennée2-97/+128
2018-03-01arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16Alex Bennée1-1/+15
2018-03-01arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16Alex Bennée3-24/+104
2018-03-01arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16Alex Bennée1-23/+57
2018-03-01arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16Alex Bennée3-1/+118
2018-03-01arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16Alex Bennée3-5/+142
2018-03-01arm/translate-a64: initial decode for simd_two_reg_misc_fp16Alex Bennée1-0/+40
2018-03-01arm/translate-a64: add FP16 x2 ops for simd_indexedAlex Bennée3-6/+76
2018-03-01arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexedAlex Bennée1-16/+66
2018-03-01arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16Alex Bennée1-75/+133
2018-03-01arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16Alex Bennée3-0/+42
2018-03-01arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16Alex Bennée3-0/+41
2018-03-01arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16Alex Bennée3-0/+69
2018-03-01arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16Alex Bennée3-0/+36
2018-03-01arm/translate-a64: initial decode for simd_three_reg_same_fp16Alex Bennée1-0/+73
2018-03-01arm/translate-a64: handle_3same_64 comment fixAlex Bennée1-2/+1
2018-03-01arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)Alex Bennée3-54/+110
2018-03-01target/arm/helper: pass explicit fpst to set_rmodeAlex Bennée4-22/+22
2018-03-01target/arm/cpu.h: add additional float_status flagsAlex Bennée3-36/+75
2018-03-01target/arm/cpu.h: update comment for half-precision valuesAlex Bennée1-0/+1
2018-03-01target/arm/cpu64: introduce ARM_V8_FP16 feature bitAlex Bennée1-0/+1
2018-02-22target/arm: Fix register definitions for VMIDR and VMPIDRPeter Maydell1-4/+4
2018-02-21target/*/cpu.h: remove softfloat.hAlex Bennée5-2/+4
2018-02-15target/arm: Implement v8M MSPLIM and PSPLIM registersPeter Maydell3-0/+69
2018-02-15target/arm: Migrate v7m.other_spPeter Maydell1-0/+11
2018-02-15target/arm: Add AIRCR to vmstate structPeter Maydell1-0/+4
2018-02-15target/arm: Implement writing to CONTROL_NS for v8MPeter Maydell1-0/+10
2018-02-15hw/intc/armv7m_nvic: Implement SCRPeter Maydell2-0/+19
2018-02-15hw/intc/armv7m_nvic: Implement cache ID registersPeter Maydell2-0/+62
2018-02-15hw/intc/armv7m_nvic: Don't hardcode M profile ID registers in NVICPeter Maydell1-0/+28
2018-02-15target/arm: Handle SVE registers when using clear_vec_highRichard Henderson1-100/+62
2018-02-15target/arm: Enforce access to ZCR_EL at translationRichard Henderson4-19/+28
2018-02-15target/arm: Suppress TB end for FPCR/FPSRRichard Henderson1-2/+2
2018-02-15target/arm: Enforce FP access to FPCR/FPSRRichard Henderson3-19/+25
2018-02-15target/arm: Remove ARM_CP_64BIT from ZCR_EL registersRichard Henderson1-4/+4
2018-02-09target/arm/translate.c: Fix missing 'break' for TT insnsPeter Maydell1-0/+1
2018-02-09target/arm/kvm: gic: Prevent creating userspace GICv3 with KVMChristoffer Dall1-0/+4
2018-02-09target/arm: Add SVE state to TB->FLAGSRichard Henderson4-1/+36
2018-02-09target/arm: Add ZCR_ELxRichard Henderson2-0/+136
2018-02-09target/arm: Add SVE to migration stateRichard Henderson1-0/+53
2018-02-09target/arm: Add predicate registers for SVERichard Henderson1-0/+12
2018-02-09target/arm: Expand vector registers for SVERichard Henderson4-28/+81
2018-02-09target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction supportArd Biesheuvel1-0/+4
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