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2023-04-10target/arm: Copy guarded bit in combine_cacheattrsRichard Henderson1-0/+1
The guarded bit comes from the stage1 walk. Fixes: Coverity CID 1507929 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230407185149.3253946-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-04-10target/arm: PTE bit GP only applies to stage1Richard Henderson1-5/+5
Only perform the extract of GP during the stage1 walk. Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230407185149.3253946-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-04-03target/arm: Fix generated code for cpreg reads when HSTR is activePeter Maydell1-0/+6
In commit 049edada we added some code to handle HSTR_EL2 traps, which we did as an inline "conditionally branch over a gen_exception_insn()". Unfortunately this fails to take account of the fact that gen_exception_insn() will set s->base.is_jmp to DISAS_NORETURN. That means that at the end of the TB we won't generate the necessary code to handle the "branched over the trap and continued normal execution" codepath. The result is that the TCG main loop thinks that we stopped execution of the TB due to a situation that only happens when icount is enabled, and hits an assertion. Explicitly set is_jmp back to DISAS_NEXT so we generate the correct code for when execution continues past this insn. Note that this only happens for cpreg reads; writes will call gen_lookup_tb() which generates a valid end-of-TB. Fixes: 049edada ("target/arm: Make HSTR_EL2 traps take priority over UNDEF-at-EL1") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1551 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230330101900.2320380-1-peter.maydell@linaro.org
2023-04-03target/arm: Fix non-TCG build failure by inlining pauth_ptr_mask()Philippe Mathieu-Daudé3-24/+16
aarch64_gdb_get_pauth_reg() -- although disabled since commit 5787d17a42 ("target/arm: Don't advertise aarch64-pauth.xml to gdb") is still compiled in. It calls pauth_ptr_mask() which is located in target/arm/tcg/pauth_helper.c, a TCG specific helper. To avoid a linking error when TCG is not enabled: Undefined symbols for architecture arm64: "_pauth_ptr_mask", referenced from: _aarch64_gdb_get_pauth_reg in target_arm_gdbstub64.c.o ld: symbol(s) not found for architecture arm64 clang: error: linker command failed with exit code 1 (use -v to see invocation) - Inline pauth_ptr_mask() in aarch64_gdb_get_pauth_reg() (this is the single user), - Rename pauth_ptr_mask_internal() as pauth_ptr_mask() and inline it in "internals.h", Fixes: e995d5cce4 ("target/arm: Implement gdbstub pauth extension") Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230328212516.29592-1-philmd@linaro.org [PMM: reinstated doc comment] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-28softmmu: Restrict cpu_check_watchpoint / address_matches to TCG accelPhilippe Mathieu-Daudé2-0/+2
Both cpu_check_watchpoint() and cpu_watchpoint_address_matches() are specific to TCG system emulation. Declare them in "tcg-cpu-ops.h" to be sure accessing them from non-TCG code is a compilation error. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230328173117.15226-2-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-28target/arm/gdbstub: Only advertise M-profile features if TCG availablePhilippe Mathieu-Daudé1-2/+3
Cortex-M profile is only emulable from TCG accelerator. Restrict the GDBstub features to its availability in order to avoid a link error when TCG is not enabled: Undefined symbols for architecture arm64: "_arm_v7m_get_sp_ptr", referenced from: _m_sysreg_get in target_arm_gdbstub.c.o "_arm_v7m_mrs_control", referenced from: _arm_gdb_get_m_systemreg in target_arm_gdbstub.c.o ld: symbol(s) not found for architecture arm64 clang: error: linker command failed with exit code 1 (use -v to see invocation) Fixes: 7d8b28b8b5 ("target/arm: Implement gdbstub m-profile systemreg and secext") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20230322142902.69511-3-philmd@linaro.org [PMM: add #include since I cherry-picked this patch from the series] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-21target/arm: Don't advertise aarch64-pauth.xml to gdbPeter Maydell1-0/+7
Unfortunately a bug in older versions of gdb means that they will crash if QEMU sends them the aarch64-pauth.xml. This bug is fixed in gdb commit 1ba3a3222039eb25, and there are plans to backport that to affected gdb release branches, but since the bug affects gdb 9 through 12 it is very widely deployed (for instance by distros). It is not currently clear what the best way to deal with this is; it has been proposed to define a new XML feature name that old gdb will ignore but newer gdb can handle. Since QEMU's 8.0 release is imminent and at least one of our CI runners is now falling over this, disable the pauth XML for the moment. We can follow up with a more considered fix either in time for 8.0 or else for the 8.1 release. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-21target/arm: Add Neoverse-N1 registersChen Baozi1-0/+69
Add implementation defined registers for neoverse-n1 which would be accessed by TF-A. Since there is no DSU in Qemu, CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition. Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Message-id: 20230313033936.585669-1-chenbaozi@phytium.com.cn Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-13target/arm: Avoid tcg_const_ptr in handle_revRichard Henderson1-11/+15
Here it is not trivial to notice first initialization, so explicitly zero the temps. Use an array for the output, rather than separate tcg_rd/tcg_rd_hi variables. Fixes a bug by adding a missing clear_vec_high. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrnRichard Henderson1-2/+6
It is easy enough to use mov instead of or-with-zero and relying on the optimizer to fold away the or. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/arm: Avoid tcg_const_ptr in disas_simd_zip_trnRichard Henderson1-20/+21
It is easy enough to use mov instead of or-with-zero and relying on the optimizer to fold away the or. Use an array for the output, rather than separate tcg_res{l,h} variables. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/arm: Avoid tcg_const_* in translate-mve.cRichard Henderson1-25/+29
All uses are in the context of an accumulator conditionally having a zero input. Split the rda variable to rda_{i,o}, and set rda_i to tcg_constant_foo(0) when required. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/arm: Avoid tcg_const_ptr in gen_sve_{ldr,str}Richard Henderson1-2/+4
This hides the implicit initialization of a variable. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/arm: Improve trans_BFCIRichard Henderson1-8/+6
Reorg temporary usage so that we can use tcg_constant_i32. tcg_gen_deposit_i32 already has a width == 32 special case, so remove the check here. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/arm: Create gen_set_rmode, gen_restore_rmodeRichard Henderson4-48/+48
Split out common subroutines for handing rounding mode changes during translation. Use tcg_constant_i32 and tcg_temp_new_i32 instead of tcg_const_i32. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/arm: Consistently use ARMFPRounding during translationRichard Henderson3-20/+20
In preparation for extracting new helpers, ensure that the rounding mode is represented as ARMFPRounding and not FloatRoundMode. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/arm: Improve arm_rmode_to_sfRichard Henderson3-29/+18
Use proper enumeration types for input and output. Use a const array to perform the mapping, with an assert that the input is valid. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/arm: Handle FPROUNDING_ODD in arm_rmode_to_sfRichard Henderson1-4/+2
While this enumerator has been present since the first commit, it isn't ever used. The first actual use of round-to-odd came with SVE, which currently uses float_round_to_odd instead of the arm-specific enumerator. Amusingly, the comment about unhandled TIEAWAY has been out of date since the initial commit of translate-a64.c. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/arm: Use rmode >= 0 for need_rmodeRichard Henderson1-28/+6
Initialize rmode to -1 instead of keeping two variables. This is already used elsewhere in translate-a64.c. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-13target/arm: Remove `NB_MMU_MODES` defineAnton Johansson1-2/+0
Signed-off-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230306175230.7110-4-anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-07gdbstub: move register helpers into standalone includeAlex Bennée4-2/+4
These inline helpers are all used by target specific code so move them out of the general header so we don't needlessly pollute the rest of the API with target specific stuff. Note we have to include cpu.h in semihosting as it was relying on a side effect before. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230302190846.2593720-21-alex.bennee@linaro.org> Message-Id: <20230303025805.625589-21-richard.henderson@linaro.org>
2023-03-06target/arm: Rewrite check_s2_mmu_setupRichard Henderson1-76/+97
Integrate neighboring code from get_phys_addr_lpae which computed starting level, as it is easier to validate when doing both at the same time. Mirror the checks at the start of AArch{64,32}.S2Walk, especially S2InvalidSL and S2InconsistentSL. This reverts 49ba115bb74, which was incorrect -- there is nothing in the ARM pseudocode that depends on TxSZ, i.e. outputsize; the pseudocode is consistent in referencing PAMax. Fixes: 49ba115bb74 ("target/arm: Pass outputsize down to check_s2_mmu_setup") Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230227225832.816605-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-06target/arm: Diagnose incorrect usage of arm_is_secure subroutinesRichard Henderson1-1/+4
In several places we use arm_is_secure_below_el3 and arm_is_el3_or_mon separately from arm_is_secure. These functions make no sense for m-profile, and would indicate prior incorrect feature testing. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230227225832.816605-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-06target/arm: Stub arm_hcr_el2_eff for m-profileRichard Henderson1-0/+3
M-profile doesn't have HCR_EL2. While we could test features before each call, zero is a generally safe return value to disable the code in the caller. This test is required to avoid an assert in arm_is_secure_below_el3. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230227225832.816605-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-06target/arm: Handle m-profile in arm_is_secureRichard Henderson1-0/+3
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1421 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230227225832.816605-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-06target/arm: Implement gdbstub m-profile systemreg and secextRichard Henderson2-0/+180
The upstream gdb xml only implements {MSP,PSP}{,_NS,S}, but go ahead and implement the other system registers as well. Since there is significant overlap between the two, implement them with common code. The only exception is the systemreg view of CONTROL, which merges the banked bits as per MRS. Signed-off-by: David Reiss <dreiss@meta.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230227213329.793795-15-richard.henderson@linaro.org [rth: Substatial rewrite using enumerator and shared code.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-06target/arm: Export arm_v7m_get_sp_ptrDavid Reiss2-43/+51
Allow the function to be used outside of m_helper.c. Move to be outside of ifndef CONFIG_USER_ONLY block. Rename from get_v7m_sp_ptr. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: David Reiss <dreiss@meta.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230227213329.793795-14-richard.henderson@linaro.org [rth: Split out of a larger patch] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-06target/arm: Export arm_v7m_mrs_controlDavid Reiss2-3/+6
Allow the function to be used outside of m_helper.c. Rename with an "arm_" prefix. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: David Reiss <dreiss@meta.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230227213329.793795-13-richard.henderson@linaro.org [rth: Split out of a larger patch] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-06target/arm: Implement gdbstub pauth extensionRichard Henderson3-0/+41
The extension is primarily defined by the Linux kernel NT_ARM_PAC_MASK ptrace register set. The original gdb feature consists of two masks, data and code, which are used to mask out the authentication code within a pointer. Following discussion with Luis Machado, add two more masks in order to support pointers within the high half of the address space (i.e. TTBR1 vs TTBR0). Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1105 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230227213329.793795-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-06target/arm: Create pauth_ptr_maskRichard Henderson2-4/+32
Keep the logic for pauth within pauth_helper.c, and expose a helper function for use with the gdbstub pac extension. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230227213329.793795-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-06target/arm: Simplify iteration over bit widthsRichard Henderson1-4/+6
Order suf[] by the log8 of the width. Use ARRAY_SIZE instead of hard-coding 128. This changes the order of the union definitions, but retains the order of the union-of-union members. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230227213329.793795-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-06target/arm: Add name argument to output_vector_union_typeRichard Henderson1-14/+14
This will make the function usable between SVE and SME. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230227213329.793795-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-06target/arm: Fix svep width in arm_gen_dynamic_svereg_xmlRichard Henderson1-1/+1
Define svep based on the size of the predicates, not the primary vector registers. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230227213329.793795-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-06target/arm: Hoist pred_width in arm_gen_dynamic_svereg_xmlRichard Henderson1-2/+3
Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230227213329.793795-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-06target/arm: Simplify register counting in arm_gen_dynamic_svereg_xmlRichard Henderson1-10/+15
Rather than increment base_reg and num, compute num from the change to base_reg at the end. Clean up some nearby comments. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230227213329.793795-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-06target/arm: Split out output_vector_union_typeRichard Henderson1-37/+44
Create a subroutine for creating the union of unions of the various type sizes that a vector may contain. Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230227213329.793795-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-06target/arm: Move arm_gen_dynamic_svereg_xml to gdbstub64.cRichard Henderson4-126/+119
The function is only used for aarch64, so move it to the file that has the other aarch64 gdbstub stuff. Move the declaration to internals.h. Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230227213329.793795-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-06target/arm: Unexport arm_gen_dynamic_sysreg_xmlRichard Henderson2-2/+1
This function is not used outside gdbstub.c. Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230227213329.793795-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-06target/arm: Normalize aarch64 gdbstub get/set function namesRichard Henderson3-12/+13
Make the form of the function names between fp and sve the same: - arm_gdb_*_svereg -> aarch64_gdb_*_sve_reg. - aarch64_fpu_gdb_*_reg -> aarch64_gdb_*_fpu_reg. Reviewed-by: Fabiano Rosas <farosas@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230227213329.793795-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-05target/arm: Drop tcg_temp_free from translator.hRichard Henderson1-2/+0
Translators are no longer required to free tcg temporaries. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-05target/arm: Drop tcg_temp_free from translator-vfp.cRichard Henderson1-193/+0
Translators are no longer required to free tcg temporaries. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-05target/arm: Drop tcg_temp_free from translator-sve.cRichard Henderson1-184/+2
Translators are no longer required to free tcg temporaries. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-05target/arm: Drop tcg_temp_free from translator-sme.cRichard Henderson1-28/+0
Translators are no longer required to free tcg temporaries. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-05target/arm: Drop tcg_temp_free from translator-neon.cRichard Henderson1-130/+1
Translators are no longer required to free tcg temporaries. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-05target/arm: Drop tcg_temp_free from translator-mve.cRichard Henderson1-52/+0
Translators are no longer required to free tcg temporaries. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-05target/arm: Drop tcg_temp_free from translator-m-nocp.cRichard Henderson1-20/+0
Translators are no longer required to free tcg temporaries. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-05target/arm: Drop tcg_temp_free from translator-a64.cRichard Henderson1-457/+11
Translators are no longer required to free tcg temporaries. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-05target/arm: Drop new_tmp_a64_zeroRichard Henderson2-24/+18
Only the use within cpu_reg requires a writable temp, so inline new_tmp_a64_zero there. All other uses are fine with a constant temp, so use tcg_constant_i64(0). Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-05target/arm: Drop new_tmp_a64Richard Henderson3-36/+30
This is now a simple wrapper for tcg_temp_new_i64. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-05target/arm: Drop DisasContext.tmp_a64Richard Henderson2-27/+1
Translators are no longer required to free tcg temporaries, therefore there's no need to record temps for later freeing. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2024-12-27 09:44:03 +0000