riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-09-01	target/arm: Implement MVE VSUB, VMUL, VABD, VMAXNM, VMINNM	Peter Maydell	4	-0/+42
2021-09-01	target/arm: Implement MVE VADD (floating-point)	Peter Maydell	6	-6/+76
2021-08-26	target/arm: Do hflags rebuild in cpsr_write()	Peter Maydell	2	-2/+13
2021-08-26	target/arm: Implement HSTR.TJDBX	Peter Maydell	6	-0/+55
2021-08-26	target/arm: Implement HSTR.TTEE	Peter Maydell	2	-2/+18
2021-08-26	target/arm: Avoid assertion trying to use KVM and multiple ASes	Peter Maydell	1	-0/+23
2021-08-26	target/arm/cpu64: Validate sve vector lengths are supported	Andrew Jones	1	-56/+45
2021-08-26	target/arm/cpu64: Replace kvm_supported with sve_vq_supported	Andrew Jones	1	-8/+11
2021-08-26	target/arm/kvm64: Ensure sve vls map is completely clear	Andrew Jones	1	-1/+1
2021-08-26	target/arm/cpu: Introduce sve_vq_supported bitmap	Andrew Jones	2	-0/+6
2021-08-25	target/arm: kvm: use RCU_READ_LOCK_GUARD() in kvm_arch_fixup_msi_route()	Hamza Mahfooz	1	-9/+8
2021-08-25	target/arm: Implement M-profile trapping on division by zero	Peter Maydell	5	-6/+26
2021-08-25	target/arm: Re-indent sdiv and udiv helpers	Peter Maydell	1	-6/+9
2021-08-25	target/arm: Implement MVE interleaving loads/stores	Peter Maydell	4	-0/+495
2021-08-25	target/arm: Implement MVE scatter-gather immediate forms	Peter Maydell	4	-36/+150
2021-08-25	target/arm: Implement MVE scatter-gather insns	Peter Maydell	4	-0/+270
2021-08-25	target/arm: Implement MVE VCTP	Peter Maydell	6	-1/+58
2021-08-25	target/arm: Implement MVE VPNOT	Peter Maydell	4	-0/+38
2021-08-25	target/arm: Implement MVE VMOV to/from 2 general-purpose registers	Peter Maydell	4	-1/+91
2021-08-25	target/arm: Implement MVE VMAXA, VMINA	Peter Maydell	4	-0/+40
2021-08-25	target/arm: Implement MVE VQABS, VQNEG	Peter Maydell	4	-0/+50
2021-08-25	target/arm: Implement MVE saturating doubling multiply accumulates	Peter Maydell	4	-0/+120
2021-08-25	target/arm: Implement MVE VMLA	Peter Maydell	4	-0/+11
2021-08-25	target/arm: Implement MVE VMLADAV and VMLSLDAV	Peter Maydell	4	-5/+150
2021-08-25	target/arm: Rename MVEGenDualAccOpFn to MVEGenLongDualAccOpFn	Peter Maydell	1	-8/+8
2021-08-25	target/arm: Implement MVE narrowing moves	Peter Maydell	4	-0/+132
2021-08-25	target/arm: Implement MVE VABAV	Peter Maydell	4	-0/+82
2021-08-25	target/arm: Implement MVE integer min/max across vector	Peter Maydell	4	-2/+150
2021-08-25	target/arm: Move 'x' and 'a' bit definitions into vmlaldav formats	Peter Maydell	1	-8/+8
2021-08-25	target/arm: Implement MVE shift-by-scalar	Peter Maydell	4	-3/+76
2021-08-25	target/arm: Implement MVE VMLAS	Peter Maydell	4	-0/+34
2021-08-25	target/arm: Implement MVE VPSEL	Peter Maydell	4	-2/+28
2021-08-25	target/arm: Implement MVE integer vector-vs-scalar comparisons	Peter Maydell	4	-12/+127
2021-08-25	target/arm: Implement MVE integer vector comparisons	Peter Maydell	4	-1/+152
2021-08-25	target/arm: Factor out gen_vpst()	Peter Maydell	1	-14/+17
2021-08-25	target/arm: Implement MVE incrementing/decrementing dup insns	Peter Maydell	4	-0/+220
2021-08-25	target/arm: Implement MVE VMULL (polynomial)	Peter Maydell	6	-5/+83
2021-08-25	target/arm: Fix VLDRB/H/W for predicated elements	Peter Maydell	1	-3/+5
2021-08-25	target/arm: Fix VPT advance when ECI is non-zero	Peter Maydell	1	-7/+17
2021-08-25	target/arm: Factor out mve_eci_mask()	Peter Maydell	1	-24/+34
2021-08-25	target/arm: Fix calculation of LTP mask when LR is 0	Peter Maydell	1	-1/+2
2021-08-25	target/arm: Fix MVE 48-bit SQRSHRL for small right shifts	Peter Maydell	1	-2/+9
2021-08-25	target/arm: Fix 48-bit saturating shifts	Peter Maydell	1	-7/+5
2021-08-25	target/arm: Fix mask handling for MVE narrowing operations	Peter Maydell	1	-1/+3
2021-08-25	target/arm: Fix signed VADDV	Peter Maydell	1	-3/+3
2021-08-25	target/arm: Fix MVE VSLI by 0 and VSRI by <dt>	Peter Maydell	1	-4/+5
2021-08-25	target/arm: Print MVE VPR in CPU dumps	Peter Maydell	1	-0/+3
2021-08-25	target/arm: Note that we handle VMOVL as a special case of VSHLL	Peter Maydell	1	-0/+2
2021-07-27	target/arm: Add sve-default-vector-length cpu property	Richard Henderson	3	-2/+77
2021-07-27	target/arm: Export aarch64_sve_zcr_get_valid_len	Richard Henderson	2	-2/+12