riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-09-21	target/arm: Remove out of date ARM ARM section references in A64 decoder	Peter Maydell	1	-113/+114
2017-09-21	nvic: Support banked exceptions in acknowledge and complete	Peter Maydell	2	-5/+18
2017-09-21	target/arm: Handle banking in negative-execution-priority check in cpu_mmu_in...	Peter Maydell	1	-5/+16
2017-09-21	nvic: Make set_pending and clear_pending take a secure parameter	Peter Maydell	2	-11/+27
2017-09-21	nvic: Implement AIRCR changes for v8M	Peter Maydell	2	-0/+19
2017-09-21	target/arm: Implement MSR/MRS access to NS banked registers	Peter Maydell	1	-0/+110
2017-09-19	arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directly	Igor Mammedov	2	-1/+4
2017-09-14	target/arm: Avoid an extra temporary for store_exclusive	Richard Henderson	1	-17/+9
2017-09-14	AArch64: Fix single stepping of ERET instruction	Jaroslaw Pelczar	1	-0/+1
2017-09-14	target/arm: Rename 'type' to 'excret' in do_v7m_exception_exit()	Peter Maydell	1	-11/+12
2017-09-14	target/arm: Add and use defines for EXCRET constants	Peter Maydell	2	-5/+19
2017-09-14	target/arm: Remove unnecessary '\| 0xf0000000' from do_v7m_exception_exit()	Peter Maydell	1	-2/+2
2017-09-14	target/arm: Get PRECISERR and IBUSERR the right way round	Peter Maydell	1	-4/+4
2017-09-14	target/arm: Clear exclusive monitor on v7M reset, exception entry/exit	Peter Maydell	4	-1/+19
2017-09-14	target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2	Peter Maydell	1	-16/+19
2017-09-14	hmp: fix "dump-quest-memory" segfault (arm)	Laurent Vivier	1	-2/+9
2017-09-07	Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170907'...	Peter Maydell	9	-118/+627
2017-09-07	target/arm: Add Jazelle feature	Portia Stephens	3	-1/+5
2017-09-07	target/arm: Implement new do_transaction_failed hook	Peter Maydell	3	-0/+54
2017-09-07	target/arm: Implement BXNS, and banked stack pointers	Peter Maydell	6	-1/+138
2017-09-07	target/arm: Move regime_is_secure() to target/arm/internals.h	Peter Maydell	2	-26/+26
2017-09-07	target/arm: Make CFSR register banked for v8M	Peter Maydell	3	-11/+17
2017-09-07	target/arm: Make MMFAR banked for v8M	Peter Maydell	3	-4/+5
2017-09-07	target/arm: Make CCR register banked for v8M	Peter Maydell	4	-7/+15
2017-09-07	target/arm: Make MPU_CTRL register banked for v8M	Peter Maydell	3	-4/+6
2017-09-07	target/arm: Make MPU_RNR register banked for v8M	Peter Maydell	4	-7/+17
2017-09-07	target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M	Peter Maydell	4	-17/+36
2017-09-07	target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M	Peter Maydell	3	-6/+10
2017-09-07	target/arm: Make VTOR register banked for v8M	Peter Maydell	3	-3/+4
2017-09-07	target/arm: Make CONTROL register banked for v8M	Peter Maydell	4	-14/+17
2017-09-07	target/arm: Make FAULTMASK register banked for v8M	Peter Maydell	3	-8/+31
2017-09-07	target/arm: Make PRIMASK register banked for v8M	Peter Maydell	3	-5/+10
2017-09-07	target/arm: Make BASEPRI register banked for v8M	Peter Maydell	3	-6/+21
2017-09-07	target/arm: Add MMU indexes for secure v8M	Peter Maydell	2	-3/+25
2017-09-07	target/arm: Register second AddressSpace for secure v8M CPUs	Peter Maydell	1	-7/+6
2017-09-07	target/arm: Add state field, feature bit and migration for v8M secure state	Peter Maydell	4	-1/+34
2017-09-07	target/arm: Implement new PMSAv8 behaviour	Peter Maydell	1	-1/+110
2017-09-07	target/arm: Implement ARMv8M's PMSAv8 registers	Peter Maydell	3	-12/+66
2017-09-06	target/arm: Perform per-insn cross-page check only for Thumb	Richard Henderson	1	-25/+33
2017-09-06	target/arm: Split out thumb_tr_translate_insn	Richard Henderson	1	-41/+80
2017-09-06	target/arm: Move ss check to init_disas_context	Richard Henderson	1	-5/+8
2017-09-06	target/arm: [a64] Move page and ss checks to init_disas_context	Richard Henderson	1	-8/+9
2017-09-06	target/arm: [tcg] Port to generic translation framework	Lluís Vilanova	3	-183/+41
2017-09-06	target/arm: [tcg,a64] Port to disas_log	Lluís Vilanova	1	-5/+14
2017-09-06	target/arm: [tcg] Port to disas_log	Lluís Vilanova	1	-5/+13
2017-09-06	target/arm: [tcg,a64] Port to tb_stop	Lluís Vilanova	1	-60/+67
2017-09-06	target/arm: [tcg] Port to tb_stop	Lluís Vilanova	1	-77/+84
2017-09-06	target/arm: [tcg,a64] Port to translate_insn	Lluís Vilanova	1	-28/+43
2017-09-06	target/arm: [tcg] Port to translate_insn	Lluís Vilanova	2	-75/+91
2017-09-06	target/arm: [tcg,a64] Port to breakpoint_check	Lluís Vilanova	1	-17/+31