| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2023-06-19 | target/arm: Convert atomic memory ops to decodetree | Peter Maydell | 2 | -98/+70 |
| 2023-06-19 | target/arm: Convert LDR/STR reg+reg to decodetree | Peter Maydell | 2 | -87/+98 |
| 2023-06-19 | target/arm: Convert LDR/STR with 12-bit immediate to decodetree | Peter Maydell | 2 | -88/+41 |
| 2023-06-19 | target/arm: Convert ld/st reg+imm9 insns to decodetree | Peter Maydell | 2 | -118/+149 |
| 2023-06-19 | target/arm: Convert load/store-pair to decodetree | Peter Maydell | 2 | -196/+249 |
| 2023-06-19 | target/arm: Convert load reg (literal) group to decodetree | Peter Maydell | 2 | -54/+35 |
| 2023-06-19 | target/arm: Convert LDXP, STXP, CASP, CAS to decodetree | Peter Maydell | 2 | -76/+50 |
| 2023-06-19 | target/arm: Convert load/store exclusive and ordered to decodetree | Peter Maydell | 2 | -62/+103 |
| 2023-06-19 | target/arm: Convert exception generation instructions to decodetree | Peter Maydell | 2 | -106/+76 |
| 2023-06-19 | target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetree | Peter Maydell | 2 | -28/+14 |
| 2023-06-19 | target/arm: Convert MSR (immediate) to decodetree | Peter Maydell | 2 | -115/+123 |
| 2023-06-19 | target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree | Peter Maydell | 2 | -27/+32 |
| 2023-06-19 | target/arm: Convert barrier insns to decodetree | Peter Maydell | 2 | -53/+46 |
| 2023-06-19 | target/arm: Convert hint instruction space to decodetree | Peter Maydell | 2 | -123/+185 |
| 2023-06-19 | target/arm: Consistently use finalize_memop_asimd() for ASIMD loads/stores | Peter Maydell | 1 | -4/+6 |
| 2023-06-19 | target/arm: Pass memop to gen_mte_check1_mmuidx() in reg_imm9 decode | Peter Maydell | 1 | -1/+1 |
| 2023-06-19 | target/arm: Return correct result for LDG when ATA=0 | Peter Maydell | 1 | -1/+5 |
| 2023-06-19 | target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomics | Peter Maydell | 1 | -2/+16 |
| 2023-06-15 | target/arm: Allow users to set the number of VFP registers | Cédric Le Goater | 2 | -0/+34 |
| 2023-06-07 | target/arm: Only include tcg/oversized-guest.h if CONFIG_TCG | Richard Henderson | 1 | -2/+3 |
| 2023-06-06 | Merge tag 'pull-target-arm-20230606' of https://git.linaro.org/people/pmaydel... | Richard Henderson | 20 | -478/+1581 |
| 2023-06-06 | target/arm: trap DCC access in user mode emulation | Zhuojia Shen | 2 | -0/+7 |
| 2023-06-06 | target/arm: allow DC CVA[D]P in user mode emulation | Zhuojia Shen | 1 | -4/+2 |
| 2023-06-06 | target/arm: Enable FEAT_LSE2 for -cpu max | Richard Henderson | 1 | -0/+1 |
| 2023-06-06 | target/arm: Move mte check for store-exclusive | Richard Henderson | 1 | -6/+36 |
| 2023-06-06 | target/arm: Relax ordered/atomic alignment checks for LSE2 | Richard Henderson | 3 | -26/+104 |
| 2023-06-06 | target/arm: Add SCTLR.nAA to TBFLAG_A64 | Richard Henderson | 4 | -1/+11 |
| 2023-06-06 | target/arm: Check alignment in helper_mte_check | Richard Henderson | 3 | -1/+22 |
| 2023-06-06 | target/arm: Pass single_memop to gen_mte_checkN | Richard Henderson | 3 | -15/+22 |
| 2023-06-06 | target/arm: Pass memop to gen_mte_check1* | Richard Henderson | 3 | -42/+49 |
| 2023-06-06 | target/arm: Hoist finalize_memop out of do_fp_{ld, st} | Richard Henderson | 1 | -20/+23 |
| 2023-06-06 | target/arm: Hoist finalize_memop out of do_gpr_{ld, st} | Richard Henderson | 1 | -26/+35 |
| 2023-06-06 | target/arm: Load/store integer pair with one tcg operation | Richard Henderson | 1 | -15/+55 |
| 2023-06-06 | target/arm: Sink gen_mte_check1 into load/store_exclusive | Richard Henderson | 1 | -23/+21 |
| 2023-06-06 | target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r | Richard Henderson | 1 | -25/+70 |
| 2023-06-06 | target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G | Richard Henderson | 1 | -7/+10 |
| 2023-06-06 | target/arm: Use tcg_gen_qemu_{st, ld}_i128 for do_fp_{st, ld} | Richard Henderson | 2 | -24/+35 |
| 2023-06-06 | target/arm: Use tcg_gen_qemu_ld_i128 for LDXP | Richard Henderson | 1 | -11/+20 |
| 2023-06-06 | target/arm: Introduce finalize_memop_{atom,pair} | Richard Henderson | 3 | -5/+37 |
| 2023-06-06 | target/arm: Add feature test for FEAT_LSE2 | Richard Henderson | 1 | -0/+5 |
| 2023-06-06 | target/arm: Add commentary for CPUARMState.exclusive_high | Richard Henderson | 1 | -0/+8 |
| 2023-06-06 | hvf: add guest debugging handlers for Apple Silicon hosts | Francesco Cagnin | 2 | -2/+479 |
| 2023-06-06 | hvf: add breakpoint handlers | Francesco Cagnin | 1 | -0/+63 |
| 2023-06-06 | hvf: handle access for more registers | Francesco Cagnin | 1 | -0/+213 |
| 2023-06-06 | arm: move KVM breakpoints helpers | Francesco Cagnin | 4 | -277/+305 |
| 2023-06-06 | atomics: eliminate mb_read/mb_set | Paolo Bonzini | 1 | -1/+1 |
| 2023-06-05 | target/arm: Add missing include of exec/exec-all.h | Richard Henderson | 1 | -0/+1 |
| 2023-06-05 | target/arm: Tidy helpers for translation | Richard Henderson | 9 | -46/+9 |
| 2023-06-05 | accel/tcg: Introduce translator_io_start | Richard Henderson | 6 | -34/+19 |
| 2023-06-05 | tcg: Split helper-proto.h | Richard Henderson | 1 | -0/+1 |
