| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2020-05-14 | target/arm: Clear tail in gvec_fmul_idx_*, gvec_fmla_idx_* | Richard Henderson | 1 | -0/+2 |
| 2020-05-14 | target/arm: Pass pointer to qc to qrdmla/qrdmls | Richard Henderson | 2 | -34/+54 |
| 2020-05-14 | target/arm: Create gen_gvec_{qrdmla,qrdmls} | Richard Henderson | 3 | -58/+33 |
| 2020-05-14 | target/arm: Remove fp_status from helper_{recpe, rsqrte}_u32 | Richard Henderson | 4 | -18/+8 |
| 2020-05-14 | target/arm: Create gen_gvec_{uqadd, sqadd, uqsub, sqsub} | Richard Henderson | 4 | -135/+147 |
| 2020-05-14 | target/arm: Create gen_gvec_{cmtst,ushl,sshl} | Richard Henderson | 4 | -102/+95 |
| 2020-05-14 | target/arm: Swap argument order for VSHL during decode | Richard Henderson | 2 | -4/+16 |
| 2020-05-14 | target/arm: Create gen_gvec_{mla,mls} | Richard Henderson | 4 | -73/+71 |
| 2020-05-14 | target/arm: Create gen_gvec_{ceq,clt,cle,cgt,cge}0 | Richard Henderson | 3 | -218/+74 |
| 2020-05-14 | target/arm: Tidy handle_vec_simd_shri | Richard Henderson | 1 | -42/+14 |
| 2020-05-14 | target/arm: Remove unnecessary range check for VSHL | Richard Henderson | 1 | -10/+2 |
| 2020-05-14 | target/arm: Create gen_gvec_{sri,sli} | Richard Henderson | 5 | -101/+160 |
| 2020-05-14 | target/arm: Create gen_gvec_{u,s}{rshr,rsra} | Richard Henderson | 5 | -26/+527 |
| 2020-05-14 | target/arm: Create gen_gvec_[us]sra | Richard Henderson | 5 | -79/+139 |
| 2020-05-14 | target/arm: Use correct GDB XML for M-profile cores | Peter Maydell | 2 | -4/+19 |
| 2020-05-11 | target/arm: Fix tcg_gen_gvec_dup_imm vs DUP (indexed) | Richard Henderson | 1 | -1/+5 |
| 2020-05-11 | target/arm: Use tcg_gen_gvec_5_ptr for sve FMLA/FCMLA | Richard Henderson | 3 | -162/+118 |
| 2020-05-11 | target/arm: Restrict TCG cpus to TCG accel | Philippe Mathieu-Daudé | 3 | -634/+665 |
| 2020-05-11 | target/arm/cpu: Restrict v8M IDAU interface to Aarch32 CPUs | Philippe Mathieu-Daudé | 1 | -1/+1 |
| 2020-05-11 | target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[] | Philippe Mathieu-Daudé | 2 | -12/+12 |
| 2020-05-11 | target/arm: Make set_feature() available for other files | Thomas Huth | 3 | -20/+10 |
| 2020-05-11 | target/arm/kvm: Inline set_feature() calls | Philippe Mathieu-Daudé | 2 | -25/+10 |
| 2020-05-11 | target/arm: Remove sve_memopidx | Richard Henderson | 3 | -26/+10 |
| 2020-05-11 | target/arm: Reuse sve_probe_page for gather loads | Richard Henderson | 1 | -113/+123 |
| 2020-05-11 | target/arm: Reuse sve_probe_page for scatter stores | Richard Henderson | 1 | -77/+117 |
| 2020-05-11 | target/arm: Reuse sve_probe_page for gather first-fault loads | Richard Henderson | 1 | -207/+138 |
| 2020-05-11 | target/arm: Use SVEContLdSt for contiguous stores | Richard Henderson | 1 | -119/+152 |
| 2020-05-11 | target/arm: Update contiguous first-fault and no-fault loads | Richard Henderson | 1 | -180/+158 |
| 2020-05-11 | target/arm: Use SVEContLdSt for multi-register contiguous loads | Richard Henderson | 1 | -144/+79 |
| 2020-05-11 | target/arm: Handle watchpoints in sve_ld1_r | Richard Henderson | 1 | -1/+71 |
| 2020-05-11 | target/arm: Use SVEContLdSt in sve_ld1_r | Richard Henderson | 1 | -91/+97 |
| 2020-05-11 | target/arm: Adjust interface of sve_ld1_host_fn | Richard Henderson | 1 | -61/+63 |
| 2020-05-11 | target/arm: Add sve infrastructure for page lookup | Richard Henderson | 1 | -2/+261 |
| 2020-05-11 | target/arm: Drop manual handling of set/clear_helper_retaddr | Richard Henderson | 1 | -38/+0 |
| 2020-05-11 | target/arm: Use cpu_*_data_ra for sve_ldst_tlb_fn | Richard Henderson | 1 | -135/+86 |
| 2020-05-11 | target/arm: Drop access_el3_aa32ns_aa64any() | Edgar E. Iglesias | 1 | -23/+7 |
| 2020-05-06 | target/arm: Use tcg_gen_gvec_dup_imm | Richard Henderson | 3 | -15/+16 |
| 2020-05-04 | target/arm: Move gen_ function typedefs to translate.h | Peter Maydell | 2 | -17/+17 |
| 2020-05-04 | target/arm: Convert Neon 3-reg-same VMUL, VMLA, VMLS, VSHL to decodetree | Peter Maydell | 3 | -25/+56 |
| 2020-05-04 | target/arm: Convert Neon 3-reg-same VQADD/VQSUB to decodetree | Peter Maydell | 3 | -12/+23 |
| 2020-05-04 | target/arm: Convert Neon 3-reg-same comparisons to decodetree | Peter Maydell | 3 | -20/+33 |
| 2020-05-04 | target/arm: Convert Neon 3-reg-same VMAX/VMIN to decodetree | Peter Maydell | 3 | -19/+21 |
| 2020-05-04 | target/arm: Convert Neon 3-reg-same logic ops to decodetree | Peter Maydell | 3 | -37/+32 |
| 2020-05-04 | target/arm: Convert Neon 3-reg-same VADD/VSUB to decodetree | Peter Maydell | 5 | -19/+68 |
| 2020-05-04 | target/arm: Convert Neon 'load/store single structure' to decodetree | Peter Maydell | 3 | -147/+100 |
| 2020-05-04 | target/arm: Convert Neon 'load single structure to all lanes' to decodetree | Peter Maydell | 3 | -53/+80 |
| 2020-05-04 | target/arm: Convert Neon load/store multiple structures to decodetree | Peter Maydell | 3 | -89/+133 |
| 2020-05-04 | target/arm: Convert VFM[AS]L (scalar) to decodetree | Peter Maydell | 3 | -106/+40 |
| 2020-05-04 | target/arm: Convert V[US]DOT (scalar) to decodetree | Peter Maydell | 3 | -12/+39 |
| 2020-05-04 | target/arm: Convert VCMLA (scalar) to decodetree | Peter Maydell | 3 | -25/+46 |
