riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-06-23	target/arm: Fix sve predicate store, 8 <= VQ <= 15	Richard Henderson	1	-1/+1
2023-06-23	target/arm: Restructure has_vfp_d32 test	Richard Henderson	1	-13/+15
2023-06-23	target/arm: Add cpu properties for enabling FEAT_RME	Richard Henderson	1	-0/+53
2023-06-23	target/arm: Implement the granule protection check	Richard Henderson	1	-17/+232
2023-06-23	target/arm: Implement GPC exceptions	Richard Henderson	4	-3/+126
2023-06-23	target/arm: Add GPC syndrome	Richard Henderson	1	-0/+10
2023-06-23	target/arm: Use get_phys_addr_with_struct for stage2	Richard Henderson	1	-10/+1
2023-06-23	target/arm: Move s1_is_el0 into S1Translate	Richard Henderson	1	-15/+12
2023-06-23	target/arm: Use get_phys_addr_with_struct in S1_ptw_translate	Richard Henderson	1	-28/+18
2023-06-23	target/arm: Handle no-execute for Realm and Root regimes	Richard Henderson	1	-6/+46
2023-06-23	target/arm: Handle Block and Page bits for security space	Richard Henderson	1	-16/+73
2023-06-23	target/arm: NSTable is RES0 for the RME EL3 regime	Richard Henderson	1	-14/+14
2023-06-23	target/arm: Pipe ARMSecuritySpace through ptw.c	Richard Henderson	1	-15/+71
2023-06-23	target/arm: Remove __attribute__((nonnull)) from ptw.c	Richard Henderson	1	-4/+2
2023-06-23	target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root}	Richard Henderson	2	-4/+29
2023-06-23	target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx	Richard Henderson	2	-13/+11
2023-06-23	target/arm: Introduce ARMSecuritySpace	Richard Henderson	2	-22/+127
2023-06-23	target/arm: Add RME cpregs	Richard Henderson	2	-0/+103
2023-06-23	target/arm: SCR_EL3.NS may be RES1	Richard Henderson	1	-0/+3
2023-06-23	target/arm: Update SCR and HCR for RME	Richard Henderson	2	-4/+11
2023-06-23	target/arm: Add isar_feature_aa64_rme	Richard Henderson	2	-0/+10
2023-06-20	meson: Replace softmmu_ss -> system_ss	Philippe Mathieu-Daudé	3	-5/+5
2023-06-19	target/arm: Convert load/store tags insns to decodetree	Peter Maydell	2	-177/+190
2023-06-19	target/arm: Convert load/store single structure to decodetree	Peter Maydell	2	-108/+127
2023-06-19	target/arm: Convert load/store (multiple structures) to decodetree	Peter Maydell	2	-108/+128
2023-06-19	target/arm: Convert LDAPR/STLR (imm) to decodetree	Peter Maydell	2	-84/+54
2023-06-19	target/arm: Convert load (pointer auth) insns to decodetree	Peter Maydell	2	-67/+23
2023-06-19	target/arm: Convert atomic memory ops to decodetree	Peter Maydell	2	-98/+70
2023-06-19	target/arm: Convert LDR/STR reg+reg to decodetree	Peter Maydell	2	-87/+98
2023-06-19	target/arm: Convert LDR/STR with 12-bit immediate to decodetree	Peter Maydell	2	-88/+41
2023-06-19	target/arm: Convert ld/st reg+imm9 insns to decodetree	Peter Maydell	2	-118/+149
2023-06-19	target/arm: Convert load/store-pair to decodetree	Peter Maydell	2	-196/+249
2023-06-19	target/arm: Convert load reg (literal) group to decodetree	Peter Maydell	2	-54/+35
2023-06-19	target/arm: Convert LDXP, STXP, CASP, CAS to decodetree	Peter Maydell	2	-76/+50
2023-06-19	target/arm: Convert load/store exclusive and ordered to decodetree	Peter Maydell	2	-62/+103
2023-06-19	target/arm: Convert exception generation instructions to decodetree	Peter Maydell	2	-106/+76
2023-06-19	target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetree	Peter Maydell	2	-28/+14
2023-06-19	target/arm: Convert MSR (immediate) to decodetree	Peter Maydell	2	-115/+123
2023-06-19	target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetree	Peter Maydell	2	-27/+32
2023-06-19	target/arm: Convert barrier insns to decodetree	Peter Maydell	2	-53/+46
2023-06-19	target/arm: Convert hint instruction space to decodetree	Peter Maydell	2	-123/+185
2023-06-19	target/arm: Consistently use finalize_memop_asimd() for ASIMD loads/stores	Peter Maydell	1	-4/+6
2023-06-19	target/arm: Pass memop to gen_mte_check1_mmuidx() in reg_imm9 decode	Peter Maydell	1	-1/+1
2023-06-19	target/arm: Return correct result for LDG when ATA=0	Peter Maydell	1	-1/+5
2023-06-19	target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomics	Peter Maydell	1	-2/+16
2023-06-15	target/arm: Allow users to set the number of VFP registers	Cédric Le Goater	2	-0/+34
2023-06-07	target/arm: Only include tcg/oversized-guest.h if CONFIG_TCG	Richard Henderson	1	-2/+3
2023-06-06	Merge tag 'pull-target-arm-20230606' of https://git.linaro.org/people/pmaydel...	Richard Henderson	20	-478/+1581
2023-06-06	target/arm: trap DCC access in user mode emulation	Zhuojia Shen	2	-0/+7
2023-06-06	target/arm: allow DC CVA[D]P in user mode emulation	Zhuojia Shen	1	-4/+2