riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-11-02	target/arm: Implement arm_cpu_record_sigsegv	Richard Henderson	4	-21/+33
2021-11-02	target/arm: Use cpu_loop_exit_sigsegv for mte tag lookup	Richard Henderson	1	-4/+2
2021-11-02	target/arm: Fixup comment re handle_cpu_signal	Richard Henderson	1	-1/+1
2021-10-15	target/arm: Drop checks for singlestep_enabled	Richard Henderson	2	-38/+8
2021-10-13	target/arm: Use cpu__mmu instead of helper__mmu	Richard Henderson	2	-47/+11
2021-10-13	accel/tcg: Move cpu_atomic decls to exec/cpu_ldst.h	Richard Henderson	1	-1/+0
2021-10-13	target/arm: Use MO_128 for 16 byte atomics	Richard Henderson	1	-4/+4
2021-10-05	tcg: Rename TCGMemOpIdx to MemOpIdx	Richard Henderson	2	-9/+9
2021-10-05	tcg: Expand MO_SIZE to 3 bits	Richard Henderson	1	-1/+1
2021-09-30	Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210930'...	Peter Maydell	5	-291/+307
2021-09-30	memory: Name all the memory listeners	Peter Xu	1	-0/+1
2021-09-30	target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML	Peter Maydell	1	-16/+40
2021-09-30	target/arm: Move gdbstub related code out of helper.c	Peter Maydell	4	-271/+277
2021-09-30	target/arm: Fix coding style issues in gdbstub code in helper.c	Peter Maydell	1	-7/+16
2021-09-30	arm: tcg: Adhere to SMCCC 1.3 section 5.2	Alexander Graf	1	-29/+6
2021-09-21	hw/core: Make do_unaligned_access noreturn	Richard Henderson	1	-1/+1
2021-09-21	include/exec: Move cpu_signal_handler declaration	Richard Henderson	1	-7/+0
2021-09-21	target/arm: Optimize MVE 1op-immediate insns	Peter Maydell	1	-5/+21
2021-09-21	target/arm: Optimize MVE VSLI and VSRI	Peter Maydell	1	-2/+2
2021-09-21	target/arm: Optimize MVE VSHLL and VMOVL	Peter Maydell	1	-8/+59
2021-09-21	target/arm: Optimize MVE VSHL, VSHR immediate forms	Peter Maydell	1	-20/+63
2021-09-21	target/arm: Optimize MVE VMVN	Peter Maydell	1	-1/+1
2021-09-21	target/arm: Optimize MVE VDUP	Peter Maydell	1	-4/+8
2021-09-21	target/arm: Optimize MVE VNEG, VABS	Peter Maydell	1	-10/+22
2021-09-21	target/arm: Optimize MVE arithmetic ops	Peter Maydell	1	-9/+11
2021-09-21	target/arm: Optimize MVE logic ops	Peter Maydell	1	-15/+36
2021-09-21	target/arm: Add TB flag for "MVE insns not predicated"	Peter Maydell	7	-9/+92
2021-09-21	target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration	Peter Maydell	1	-0/+13
2021-09-21	target/arm: Avoid goto_tb if we're trying to exit to the main loop	Peter Maydell	1	-1/+33
2021-09-21	hvf: arm: Add rudimentary PMC support	Alexander Graf	1	-0/+179
2021-09-21	arm: Add Hypervisor.framework build target	Alexander Graf	2	-0/+5
2021-09-21	hvf: arm: Implement PSCI handling	Alexander Graf	3	-7/+139
2021-09-21	hvf: arm: Implement -cpu host	Peter Maydell	5	-6/+124
2021-09-21	arm/hvf: Add a WFI handler	Peter Collingbourne	1	-0/+79
2021-09-20	hvf: Add Apple Silicon support	Alexander Graf	2	-0/+804
2021-09-20	arm: Move PMC register definitions to internals.h	Alexander Graf	2	-44/+44
2021-09-20	target/arm: Consolidate ifdef blocks in reset	Peter Maydell	1	-12/+10
2021-09-20	target/arm: Always clear exclusive monitor on reset	Peter Maydell	1	-3/+3
2021-09-20	target/arm: Don't skip M-profile reset entirely in user mode	Peter Maydell	1	-0/+19
2021-09-14	target/arm: Restrict cpu_exec_interrupt() handler to sysemu	Philippe Mathieu-Daudé	3	-7/+9
2021-09-14	accel/tcg: Add DisasContextBase argument to translator_ld*	Ilya Leoshkevich	3	-11/+12
2021-09-13	target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn	Richard Henderson	1	-115/+109
2021-09-13	target/arm: Take an exception if PSTATE.IL is set	Peter Maydell	7	-0/+49
2021-09-13	hw/arm/virt: add ITS support in virt GIC	Shashi Mallela	1	-2/+2
2021-09-13	hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM	Marc Zyngier	1	-1/+6
2021-09-01	target-arm: Add support for Fujitsu A64FX	Shuuichirou Ishii	1	-0/+48
2021-09-01	target/arm: Enable MVE in Cortex-M55	Peter Maydell	1	-5/+2
2021-09-01	target/arm: Implement MVE VRINT insns	Peter Maydell	4	-0/+93
2021-09-01	target/arm: Implement MVE VCVT between single and half precision	Peter Maydell	4	-0/+108
2021-09-01	target/arm: Implement MVE VCVT with specified rounding mode	Peter Maydell	4	-0/+105